3D IC Package Structure With Redistribution Routing and Encapsulation
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Solution Overview
Problem
Existing semiconductor device packaging methods face challenges in efficiently integrating and connecting multiple components, particularly in 3D packaging and 3DIC structures, which affect yield and increase costs.
Innovation Solution
A manufacturing method involving a carrier with a de-bonding layer and insulating layer, followed by the formation of a redistribution structure, conductive pillars, and integrated circuit components, with encapsulation and planarization, and finally connecting passive components through a redistribution structure, ensuring precise electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional packaging methods are used for 3D packaging and 3DIC structures, then manufacturing complexity is reduced, but integration efficiency and connectivity of multiple components deteriorate
Solution Approach 1:
The packaging structure is divided into multiple functional layers including carrier substrate, insulating layer, de-bonding layer, and redistribution structure. Each layer performs a specific function, allowing complex 3D integration to be achieved through systematic segmentation of manufacturing steps and structural components.
Solution Approach 2:
The patent transitions from traditional 2D packaging to 3D packaging by stacking multiple semiconductor chips and passive components in vertical layers. The redistribution structure enables electrical connections between different vertical levels, achieving high-density integration through three-dimensional spatial arrangement.
2Productivity
If complex 3D packaging structures are implemented, then component integration and connectivity improve, but manufacturing yield deteriorates due to increased process difficulty
Solution Approach 1:
The de-bonding layer is formed in advance between the carrier substrate and insulating layer, enabling easy separation of the semiconductor chip from the carrier after processing. This preliminary preparation simplifies subsequent manufacturing steps and reduces process complexity, thereby improving manufacturing yield.
Solution Approach 2:
The de-bonding layer serves as an intermediary between the carrier substrate and the semiconductor chip structure. It facilitates controlled separation and enables repositioning or removal of the chip without damaging other components, thus improving manufacturing reliability and yield.
3Productivity
If multiple components are integrated in 3D structures, then connectivity and electrical connections improve, but manufacturing costs increase
Solution Approach 1:
Multiple functional elements including semiconductor chips, passive components, and redistribution structures are merged into a single integrated package. This consolidation achieves high-density electrical connections while reducing the number of separate assembly steps and materials required, thereby lowering overall manufacturing costs.
Solution Approach 2:
The redistribution structure serves multiple functions simultaneously: it provides electrical interconnections between chips, enables signal routing, and facilitates thermal management. This multi-functionality reduces the need for additional specialized components and processes, lowering manufacturing complexity and cost.
Data Source
AI summary
A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.