3D IC Package Structure With Dummy Dies to Reduce Warpage

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in bonding integrated circuit chips directly onto substrates due to increased density and corresponding decrease in area, leading to limitations in three-dimensional packaging.

Innovation Solution

The method involves forming a 3DIC structure by bonding IC dies to a wafer using hybrid bonding, incorporating dummy structures to manage scribe lines and reduce warpage, and subsequently singulating the wafer to form individual stacked IC structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If integrated circuit chips are bonded directly onto substrates, then bonding simplicity is maintained, but packaging density and three-dimensional integration are limited

Engineering Contradiction:

Improvepackaging structureVSAvoidintegration density

Core Design Contradiction:

Device complexityVSQuantity of substance

Solution Approach 1:

The patent transitions from two-dimensional planar packaging to three-dimensional stacked packaging by bonding multiple IC chips vertically onto a single substrate. This dimensional change allows significantly higher integration density without increasing the substrate footprint, resolving the contradiction between packaging simplicity and integration density.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple IC chips are nested vertically in a stacked configuration on the substrate, with each chip positioned above the previous one. This nesting approach maximizes the use of vertical space, enabling high-density integration while maintaining a compact overall structure.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Quantity of substance

If multiple IC chips are stacked in three-dimensional configuration, then integration density is improved, but warpage and stress from thermal expansion mismatch increase

Engineering Contradiction:

Improveintegration densityVSAvoidstructural stability

Core Design Contradiction:

Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The substrate is designed with uniform material composition and matched thermal expansion coefficients to those of the stacked IC chips. This homogeneity in thermal properties minimizes differential expansion and contraction during temperature cycles, reducing warpage and maintaining structural stability in the three-dimensional package.

Inventive Principle:

Principle #33Homogeneity

Solution Approach 2:

The substrate employs composite material construction with layers specifically selected to provide mechanical support and thermal expansion matching. This composite structure compensates for the inherent warpage tendencies of stacked configurations while preserving the high integration density benefits.

Inventive Principle:

Principle #40Composite materials

3Quantity of substance

If IC chip area is reduced to increase density, then integration density is improved, but direct bonding capability deteriorates

Engineering Contradiction:

Improveintegration densityVSAvoidbonding process

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

A substrate with enlarged bond pads and redistribution circuits serves as an intermediary between the small-area IC chips and the bonding process. The substrate's larger surface area provides adequate bonding area despite the chips' reduced size, enabling reliable bonding while maintaining high integration density through vertical stacking.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The bonding function is segmented between the IC chips and the substrate. The chips provide computational functionality with minimal bonding area requirements, while the substrate provides the bonding interface with sufficient area for reliable attachment. This segmentation allows small chips to be bonded effectively through the substrate's mediating bonding pads.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables efficient three-dimensional integration of IC components, reduces warpage and stress caused by thermal expansion mismatch, and enhances production yield and cost-effectiveness.

Implementation Method 1

bonding IC dies to a wafer using hybrid bonding

Methodology Applied

Scientific EffectHybrid bonding:

Implementation Method 2

reduces warpage and stress caused by thermal expansion mismatch

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20250040254A1Package structures

Publication Date: 2025.01.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.