3D Integrated Circuit Package Without Wire Bonds
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Solution Overview
Problem
The miniaturization of implantable medical devices (IMDs) requires more compact and efficient electronic circuitry, which existing packaging technologies struggle to achieve due to size constraints and the need for reduced parasitic inductance and resistive losses.
Innovation Solution
The development of an integrated circuit package with a substrate featuring a core layer between dielectric layers, where dies are disposed in cavities within the core layer, eliminating the need for wire bonds and allowing for higher frequency operation and reduced power loss, and enabling a three-dimensional high-voltage stack structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional wire bond packaging is used, then electrical connection is achieved, but parasitic inductance and resistive losses increase
Solution Approach 1:
The patent extracts and eliminates the wire bond interconnect layer from the packaging structure, directly connecting the die to the substrate contact pads through recesses in the substrate surface. This removal of the wire bond element directly reduces parasitic inductance and resistive losses while simplifying the overall packaging structure.
Solution Approach 2:
The patent transitions from a planar wire bond connection to a three-dimensional structure where dies are positioned in recesses of the substrate, creating direct vertical or near-vertical electrical pathways. This dimensional change eliminates the need for wire bonds and reduces the electrical path length, thereby reducing parasitic inductance and resistance.
2Volume of moving object
If device dimensions are reduced for miniaturization, then IMD size decreases, but heat dissipation becomes more difficult
Solution Approach 1:
The patent segments the substrate into multiple recesses that can accommodate multiple dies, allowing heat to be distributed across multiple contact points with the substrate. This segmentation enables better heat dissipation in a compact package by creating multiple thermal pathways rather than concentrating heat in a single location.
Solution Approach 2:
By positioning dies in recesses of the substrate, the patent creates direct thermal contact between the die and substrate in the vertical dimension, improving heat transfer efficiency. This three-dimensional arrangement allows heat to conduct directly from the die into the substrate without requiring large lateral heat spread areas, enabling effective heat dissipation in miniaturized devices.
3Volume of moving object
If reconstituted wafer packaging is used, then thinner and smaller electronic packages are produced, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates contact pads and recesses directly into the substrate during substrate fabrication, before die attachment. This preliminary formation of the substrate structure with integrated mounting features simplifies subsequent die attachment processes and eliminates the need for complex post-substrate processing steps required by traditional reconstituted wafer packaging methods.
Data Source
Figure 1~2
Figure 3A~3E
Figure 3F~3I
AI summary
Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.