3D Interconnect Packaging Around ICs for Broadband RF Links
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Solution Overview
Problem
Current methods for integrating integrated circuits and interconnect packaging in high-frequency electronic devices, such as bond-wiring and flip-chip processes, suffer from inductive discontinuities and fragility, limiting performance and reworkability.
Innovation Solution
An additively manufactured interconnect packaging structure is created using a 3-D printer, which forms a cavity around integrated circuits, deposits conductive transmission lines and interconnects, and uses aerosol jet deposition of dielectric materials to reduce size and enhance tolerances, allowing for efficient and effective high-frequency broadband connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bond-wiring is used to connect integrated circuits to interconnect packaging, then electrical connections are established, but inductive discontinuities are introduced in the signal path which hinder high-frequency performance
Solution Approach 1:
The patent merges the interconnect packaging structure with the integrated circuit substrate to form a unified structure. The conductive transmission lines are deposited directly onto the substrate surrounding the integrated circuit, eliminating the need for separate bond-wiring connections and thereby removing the inductive discontinuities that plague traditional approaches.
Solution Approach 2:
The patent extracts and eliminates the bond-wiring connection method entirely. By using direct aerosol jet deposition of conductive transmission lines onto the substrate, the harmful bond-wiring process is removed from the system, preventing the introduction of inductive discontinuities in the first place.
2Ease of manufacture
If flip-chip process is used to integrate integrated circuits, then connections are established, but the structure becomes fragile and not conducive to rework since connections are less accessible once bonded
Solution Approach 1:
Instead of bonding the integrated circuit to the packaging structure (flip-chip approach), the patent inverts the approach by forming the packaging structure around the integrated circuit with conductive transmission lines deposited onto it. This makes the connections accessible from the top surface rather than requiring bottom-side bonding, enabling reworkability while maintaining integration efficiency.
3Manufacturing precision
If traditional manufacturing methods are used for interconnect packaging, then structures are formed, but the size is larger and tolerances between components are looser
Solution Approach 1:
The patent replaces traditional mechanical manufacturing methods (such as photolithography and etching) with aerosol jet deposition technology. This enables direct digital deposition of conductive transmission lines with precise control over geometry and placement, achieving tight tolerances and miniaturization without the limitations of conventional mechanical manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables ultra-high frequency broadband interconnects suitable for high-power applications without requiring complex design matching networks, while maintaining thermal performance and allowing for tight component tolerances.
Implementation Method 1
aerosol jet deposition of the dielectric materials, the transmission lines and the interconnects reduces the overall size of the interconnect packaging structure while allowing for tight tolerances between the components
Data Source
AI summary
A method of manufacturing an interconnect packaging structure is provided. In one aspect, the method includes forming a first body defining a cavity around at least one integrated circuit using an additive manufacturing machine, depositing a conductive transmission line on the first body and electrically coupling the conductive transmission line and the at least one integrated circuit with a conductive interconnect.