3D IC Packaging with Through-Substrate Interconnects and Wirebonds
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Solution Overview
Problem
Fan-out Wafer Level Packaging (FOWLP) struggles to accommodate the formation of interconnect structures other than bond wires, such as wirebond structures, in three-dimensional (3D) microelectronic packages, limiting the versatility and efficiency of interconnection in compact electronic devices.
Innovation Solution
A substrate with through-substrate interconnect structures is attached to a temporary carrier, with IC dies attached in a stacked arrangement using epoxy, and wirebonds formed between the active surface of one IC die and the package substrate, followed by encapsulation and a build-up interconnect stack formation, including external interconnects like solder balls, to create a robust and compact 3D package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FOWLP uses build-up processes for package interconnections, then external interconnects can be formed, but formation of other interconnect structures such as wirebond structures is not easily accommodated
Solution Approach 1:
The patent divides the packaging process into distinct segments: first forming the stacked die structure with epoxy, then separately forming wirebond interconnects, and finally forming the build-up interconnect stack. This segmentation allows each interconnect type to be formed using its optimal process without interfering with others, resolving the contradiction between versatility and manufacturing complexity.
Solution Approach 2:
The patent transitions from traditional 2D planar packaging to 3D stacked packaging by vertically arranging multiple IC dies. This dimensional change enables compact packaging while accommodating multiple interconnect types (wirebonds, solder balls) in different spatial dimensions, thereby increasing interconnect structure versatility without proportionally increasing manufacturing complexity.
2Volume of moving object
If multiple IC dies are stacked vertically in 3D arrangement, then package compactness is improved, but interconnection complexity increases
Solution Approach 1:
The patent implements a nested structure where multiple IC dies are stacked vertically with each die containing its own integrated circuit. The dies are nested within a common package substrate, with interconnect structures (wirebonds, solder balls) nested between and around the dies. This nesting achieves compact volume while organizing complexity in a hierarchical manner.
Solution Approach 2:
The patent introduces an epoxy material as an intermediary between stacked IC dies to provide both mechanical bonding and electrical isolation. This intermediary simplifies the interconnection complexity by providing a standardized interface between dies, enabling vertical stacking without requiring complex direct inter-die bonding structures.
3Strength
If IC dies are attached using epoxy, then mechanical bonding is achieved, but electrical isolation requirements must be met
Solution Approach 1:
The patent applies epoxy with specific local properties: it provides strong mechanical bonding strength for die attachment while simultaneously providing electrical isolation between stacked dies. The epoxy's dual functionality addresses both bonding strength and electrical isolation requirements through its material composition and placement strategy between adjacent dies.
Data Source
AI summary
A package substrate having an opening and through-substrate interconnect structures is attached to a temporary carrier such as an adhesive film. The active surface of an IC die is placed in contact with the carrier substrate within the opening, to temporarily attach the die to the carrier substrate. Another die is attached to the side of the first die furthest from the carrier substrate. In one embodiment, the dies are attached to each other using an epoxy so that their respective non-active surfaces face each other. Bond wires are connected between interconnects at the active surface of the second die and the substrate. The wires are then encapsulated. After removal of the carrier substrate, a build-up interconnect structure is formed that includes external interconnects of the package substrate, such as solder balls of a ball grid array package.