3D IC Panel Bonding for Yield and Cost Trade-offs

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Solution Overview

Problem

Current 3D semiconductor fabrication methods face challenges in balancing assembly cost and product yield, with wafer-to-wafer bonding reducing yield due to non-selective die alignment and die-to-wafer/die-to-die assembly being costly with high yield, necessitating a method that optimizes these factors.

Innovation Solution

The method involves sawing a first wafer into panels of multiple die, aligning and bonding them to a second wafer, allowing for reduced placement numbers while maintaining the ability to screen and selectively bond good die, thus achieving a cost-effective compromise between high assembly cost and low yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If wafer-to-wafer bonding is used, then assembly cost is reduced, but product yield decreases due to non-selective die alignment

Engineering Contradiction:

Improveassembly costVSAvoidproduct yield

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The first wafer is divided into multiple die panels, each containing multiple die. This segmentation allows the system to process and align panels rather than individual die, reducing the number of alignment operations while maintaining the ability to select good die within each panel for bonding to the second wafer.

Inventive Principle:

Principle #1Segmentation

2Reliability

If die-to-wafer or die-to-die assembly is used, then product yield is maintained through selective bonding, but assembly cost increases due to high number of placements required

Engineering Contradiction:

Improveproduct yieldVSAvoidassembly cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

Multiple die are grouped into panels that are processed and bonded together as units. This merging approach combines the benefits of selective bonding (maintaining yield) with reduced operation count (lowering cost), as entire panels are aligned and bonded in fewer operations compared to individual die placement.

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If wafer-to-wafer bonding is used, then number of placements is reduced, but ability to selectively bond good die is lost

Engineering Contradiction:

Improvenumber of placementsVSAvoidselective bonding capability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system applies different levels of quality control at different stages: panels are processed as units for efficient alignment, but individual die within panels can still be selected based on quality metrics. This local quality approach maintains selective bonding capability while achieving the productivity benefits of reduced placement operations.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS7622313B2Fabrication of three dimensional integrated circuit employing multiple die panels

Publication Date: 2009.11.24 NXP USA INC

AI summary

A method of assembling an electronic device includes testing a first wafer of first die to identify the location of functional first die and dividing the first wafer into a set of panels, wherein a panel includes an M×N array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an M×N array of second die in the second wafer. The panel stack is sawed into a devices comprising a first die bonded to a second die. Dividing the first wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.