3D IC Parasitic Extraction for Backside and Hybrid Bonding Interfaces
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Solution Overview
Problem
Current EDA tools are unable to fully extract parasitic parameters of a 3D IC, particularly at hybrid bonding interfaces and the backside of the wafer, limiting their application in 3D IC design.
Innovation Solution
A method involving merging layouts of multiple dies and a backside circuit into a common layout, creating common and respective LVS and LPE files, and merging these into a netlist to extract complete parasitic parameters, including those at bonding interfaces and the backside circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current EDA tools are used to extract parasitic parameters, then the extraction process is simple and existing tools can be used, but the extraction is incomplete and cannot handle backside circuits and hybrid bonding interfaces
Solution Approach 1:
The patent segments the 3D IC into multiple dies with frontside and backside circuits, and extracts parasitic parameters for each segment separately before integrating them into a complete netlist. This allows existing EDA tools to process each die independently while achieving complete extraction across the entire 3D IC structure.
Solution Approach 2:
The patent merges the parasitic parameter extractions from multiple dies and backside circuits into a single comprehensive netlist. By combining the extracted parameters from all segments and integrating them with the interconnect models, the tool achieves complete parasitic parameter extraction for the entire 3D IC without requiring new EDA tools.
2Manufacturing precision
If parasitic parameters of all dies and backside circuits are extracted, then complete design accuracy is achieved, but the extraction process becomes more complex and time-consuming
Solution Approach 1:
The extraction process is divided into separate steps for each die and backside circuit, allowing parallel processing. Each segment can be extracted independently using existing EDA tools, and the results are then combined, significantly reducing total extraction time while maintaining complete design accuracy.
Solution Approach 2:
The patent performs preliminary extraction of parasitic parameters for each die and backside circuit before final integration. By preparing the extracted parameters in advance and organizing them in a standardized format, the final merging process becomes faster and more efficient, reducing overall extraction time while ensuring complete accuracy.
Data Source
AI summary
A method of extracting parasitic parameters of a 3D IC, including steps of merging respective layouts of multiple dies and backside layout of a 3D IC into a common layout, establishing a common LVS file and a common LPE file for those dies and backside layout based on the common layout, establishing respective LVS files and respective LPE files for every die based on the respective layouts, creating a common netlist from the common LVS file and common LPE file, creating corresponding respective netlists from the respective LVS files and respective LPE files, merging the common netlist and respective netlists into a netlist, and extracting common parasitic parameters of the dies from the netlist.