3D IC Partitioning via 2D EDA Intermediary
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Solution Overview
Problem
Existing electronic design automation (EDA) tools are primarily designed for two-dimensional integrated circuits (2DICs) and lack support for three-dimensional integrated circuits (3DICs, leading to inefficient partitioning and inter-tier via connections in 3DIC designs, as they do not consider tier-specific characteristics such as thermal effects and the potential benefits of inter-tier vias over horizontal wiring.
Innovation Solution
A method that extracts design characteristics from a 2DIC design to partition components into tiers and determine inter-tier via locations, using existing 2DIC EDA tools to generate a 2D representation of a 3DIC design, allowing for improved partitioning and placement optimization that accounts for connectivity, thermal behavior, and inter-tier via efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing 2DIC EDA tools are used for 3DIC design, then development costs are reduced and tool availability is improved, but partitioning efficiency and inter-tier via optimization deteriorate because the tools do not consider tier-specific characteristics
Solution Approach 1:
The patent segments the 3DIC design process into distinct phases: extracting design characteristics from 2DIC layout, partitioning components into tier-specific groups based on those characteristics, and determining inter-tier via locations. This segmentation allows 2DIC tools to be reused for characteristic extraction while adding specialized 3DIC optimization steps for partitioning and via placement, thus maintaining cost efficiency while improving partitioning efficiency.
Solution Approach 2:
The patent introduces an intermediary processing layer that bridges 2DIC EDA tools and 3DIC design requirements. This intermediary extracts design characteristics from 2DIC layouts and uses them to guide 3DIC partitioning and via placement, enabling the reuse of existing 2DIC tools while achieving optimized 3DIC designs that consider thermal effects and inter-tier connectivity.
2Device complexity
If components are partitioned without considering tier-specific characteristics, then design simplicity is maintained, but signal propagation delay increases due to suboptimal inter-tier via placement
Solution Approach 1:
The patent applies local quality by determining inter-tier via locations based on specific design characteristics extracted from the 2DIC layout, such as connectivity patterns and thermal zones. Instead of uniform partitioning, the method optimizes via placement locally according to the functional and thermal requirements of different regions, reducing signal propagation delay without requiring complex manual design interventions.
Solution Approach 2:
The patent performs preliminary extraction of design characteristics from the 2DIC layout before partitioning components into tiers. By pre-identifying connectivity patterns, critical paths, and thermal zones in the 2DIC design, the method enables optimized 3DIC partitioning and via placement that minimizes signal propagation delay while maintaining design simplicity through automated processing.
3Ease of operation
If inter-tier vias are not optimized based on extracted design characteristics, then design process simplicity is maintained, but connectivity efficiency and thermal management performance deteriorate
Solution Approach 1:
The patent implements feedback by extracting design characteristics from the 2DIC layout and using those characteristics to guide 3DIC partitioning and inter-tier via placement. The extracted characteristics serve as feedback information that informs the optimization process, enabling automated determination of via locations that improve connectivity efficiency and thermal management while maintaining design process simplicity through systematic, rule-based optimization.
Data Source
AI summary
A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.