3D Integrated Circuit Power Distribution via Peripheral Switches
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Solution Overview
Problem
Conventional 3D integrated circuit (3D-IC) architectures face challenges in power distribution network (PDN) design, thermal management, and testing methodology, including routing congestion, heat dissipation, and impractical pre-packaging die testing.
Innovation Solution
A 3D-IC architecture that incorporates dies on different geometric planes with peripheral switches for power and signal routing, utilizing interposers for horizontal and vertical connections, enabling dynamic reconfiguration of power and test signals, and integrating voltage control circuits to improve heat dissipation and testing feasibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power rails are used to supply power from the bottom of the IC to the top in a conventional pyramid-shaped PDN, then power distribution is achieved, but significant die area is occupied and routing congestion occurs
Solution Approach 1:
The patent transitions from a conventional 2D pyramid-shaped PDN to a 3D power distribution architecture where power rails extend through multiple die layers vertically. Power supply paths are established in the third dimension through TSVs and inter-layer connections, allowing power to be distributed from bottom to top dies without occupying excessive area on any single die plane.
Solution Approach 2:
The PDN is segmented across multiple independent die layers, with each die containing its own power rails and distribution network. This segmentation allows power to be distributed locally on each die rather than requiring extensive routing on a single die, reducing the PDN area footprint while maintaining power distribution capability.
2Productivity
If multiple dies are stacked together in a fully stacked 3D architecture, then integration density is improved, but heat dissipation becomes difficult especially for bottom dies
Solution Approach 1:
The patent introduces an interposer layer as an intermediary between stacked dies. This interposer serves as a thermal management interface that can conduct heat away from the die stack, particularly from bottom dies that are hardest to cool. The interposer provides additional thermal pathways without compromising the vertical integration density of the 3D stack.
Solution Approach 2:
The die stack is segmented with spacing and intermediate layers that allow thermal management. Rather than tightly stacking all dies, the architecture incorporates thermal vias, heat spreaders, and spacing layers that create thermal pathways, enabling heat to escape from internal and bottom dies while maintaining high integration density.
3Device complexity
If dies are fully stacked together, then routing congestion is reduced, but testing of dies before packaging becomes difficult or impossible
Solution Approach 1:
The interposer layer serves as a testing intermediary that provides access points to internal dies before final packaging. Test signals can be routed through the interposer to reach TSVs and internal die structures, enabling pre-packaging testing of through-silicon via connections and die-to-die interfaces without requiring the complete packaged assembly.
Solution Approach 2:
Testing capabilities are built into the architecture before final packaging by incorporating test access mechanisms through the interposer and TSV structures. This allows preliminary testing of critical interconnections and die functionality to be performed on individual dies or partial stacks before committing to final packaging, enabling fault detection and recovery procedures to be established in advance.
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A three-dimensional integrated circuit (3D-IC) architecture incorporates multiple layers, each layer including at least one die and at least one switch to connect the dies on the different layers. In some aspects, a power distribution network (PDN) is routed from a first layer through the switches to supply power to at least one other layer, thereby reducing routing congestion on the layers. The switches can be placed around the periphery of an IC package to improve heat dissipation (e.g., by improving heat transfer from the center to the edge of the IC package). The switches can be used for routing test signals and/or other signals between layers, thereby improving test functionality and/or fault recovery.