3D IC Physical Connection Netlist via TSV and Bump Pin Segmentation
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Solution Overview
Problem
Current electronic design automation (EDA) tools face challenges in supporting 3D integrated circuit (IC) design due to the complexity of physical connections required for logical connections across multiple dies in a 3D stack, where a single physical net is insufficient to connect logic modules across different tiers, necessitating the use of through-silicon-vias (TSVs) and bump pins, and maintaining relationships between logical and physical nets is crucial.
Innovation Solution
An electronic design automation method and system that creates a physical connection netlist for a pre-floorplan partitioned 3D IC design by processing pairs of dies to establish physical connections using through-silicon vias, bump pins, and intra/inter-die nets, minimizing the number of visited dies and utilizing a die graph to select die paths, thereby forming efficient inter- and intra-die connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single physical net is used to connect logic modules across different tiers in 3D ICs, then the design is simpler, but the connection cannot be realized across multiple dies
Solution Approach 1:
The patent segments the physical connection into multiple components: intra-die nets for connections within a single die, and inter-die nets for connections across different dies. This segmentation allows the connection to be realized across multiple tiers by breaking down the complex through-die connection into manageable segments that can be implemented with standard TSV and bump pin technologies.
2Reliability
If complex physical connections with TSVs and bump pins are used to connect across multiple dies, then connection realizability is achieved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary layer of abstraction called the physical connection netlist that maps logical nets to physical components (TSVs, bump pins, intra-die nets, inter-die nets). This intermediary representation simplifies the complexity by providing a structured framework that automatically manages the complex mappings between logical and physical domains, reducing the burden on designers.
Solution Approach 2:
The patent performs preliminary actions by pre-defining the physical connection structures (TSV locations, bump pin assignments, intra-die net routing) during the physical connection netlist generation phase, before actual implementation. This preliminary planning allows for optimization of connection paths and reduces complexity during subsequent implementation stages.
3Adaptability or versatility
If logical nets are mapped to physical connections across multiple dies, then connection functionality is achieved, but maintaining relationships between logical and physical nets becomes difficult
Solution Approach 1:
The patent creates a universal physical connection netlist format that can represent multiple types of connections (intra-die, inter-die, TSV, bump pin) using a unified structure. This universal representation maintains the relationships between logical and physical nets through consistent naming conventions and hierarchical organization, making it easier to manage complex mappings across different die configurations and connection types.
Data Source
AI summary
An electronic design automation method implemented in a computing system is provided for creating a physical connections netlist for a pre-floorplan partitioned design file of 3D integrated circuits. The inputs are a 3D stack defining the topology of multiple dies, and a given design partitioning. The design partitioning defines the logic implemented in each die. The method identifies through-silicon-vias (TSVs), bump pins (BPs) and net connections.