3D IC Pick-and-Place Assembly for Nanoscale Alignment
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Solution Overview
Problem
Conventional semiconductor manufacturing faces challenges in scaling beyond 20 nm features due to physical, material, power-thermal, and technological limitations, leading to increased production costs and decreased performance without commensurate gains, and there are issues with hardware security and intellectual property violations in the supply chain.
Innovation Solution
The use of nano-precise pick-and-place assembly techniques, including the integration of prefabricated blocks (PFBs) and buried sacrificial layers, along with nano-scale airflow modeling and moiré-based alignment metrology, to enable ultra-high density heterogenous integration and secure fabrication across trusted and untrusted foundries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used to pattern sub-20 nm features, then transistor scaling continues, but production cost increases significantly and manufacturing precision deteriorates due to complex multiple-patterning requirements
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D vertically-channel transistors, moving the scaling dimension from lateral to vertical. This allows continued miniaturization without the sub-20 nm photolithography challenges, as the channel length is defined by vertical etching rather than lateral patterning, thereby maintaining manufacturing ease while improving precision.
Solution Approach 2:
The patent replaces the photolithography-based patterning mechanism with a self-aligned nanoscale printing mechanism. The nanoscale print head directly deposits material to form patterns without requiring complex optical systems, multiple patterning steps, or EUV exposure tools, significantly reducing production cost while achieving sub-20 nm precision.
2Productivity
If transistor size is reduced to increase density, then more transistors fit on chip, but power density increases and thermal management becomes difficult
Solution Approach 1:
The patent arranges transistor channels vertically in three dimensions rather than horizontally in two dimensions. This 3D configuration increases transistor density without proportionally increasing power density, as the vertical stacking allows for better thermal pathways and reduced current crowding effects that occur in planar scaling.
Solution Approach 2:
The patent implements localized material properties within the vertical channel structure, including graded doping profiles and segmented channel regions with different materials. This allows optimization of carrier transport in each region while managing heat generation locally, preventing hotspots and improving overall thermal management.
3Manufacturing precision
If feature size is reduced below 20 nm, then transistor performance improves, but tunneling and leakage currents increase negatively impacting functionality
Solution Approach 1:
The patent employs composite material structures in the vertical channel, combining different semiconductor materials (e.g., SiGe, III-V compounds) with insulating materials. This composite approach enables bandgap engineering to suppress tunneling and leakage currents while maintaining the electric field confinement needed for high performance at sub-20 nm dimensions.
Solution Approach 2:
The patent applies different material compositions and doping concentrations at different positions within the vertical channel structure. The channel region has optimized properties for carrier transport, while barrier regions have properties designed to suppress tunneling, allowing simultaneous achievement of high performance and low leakage at sub-20 nm scales.
4Manufacturing precision
If advanced patterning techniques are adopted to achieve sub-20 nm features, then manufacturing precision improves, but device complexity and process steps increase
Solution Approach 1:
The patent replaces complex optical patterning systems with a direct nanoscale printing mechanism. The nanoscale print head writes patterns directly onto the substrate using material deposition, eliminating the need for photolithography, multiple patterning steps, alignment systems, and optical exposure tools, thereby reducing device complexity while achieving sub-20 nm precision.
Solution Approach 2:
The nanoscale printing process is self-aligned, where the print head automatically positions features based on previously deposited structures without requiring external alignment systems or complex registration processes. This self-service capability eliminates multiple patterning steps and reduces process complexity while maintaining high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of 3D integrated circuits and Microscale Modular Assembled ASICs with nano-meter precision, addressing scaling challenges and ensuring hardware security while reducing production costs and intellectual property risks.
Implementation Method 1
the precision overlay is enabled by a fluid deployed between the one or more die and the product substrate
Implementation Method 2
performing plasma treatment of the one or more die
Implementation Method 3
polishing one or more source wafers using chemical mechanical polishing
Data Source
AI summary
Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.