3D IC Pick-and-Place Assembly Beyond Lithography Field Limits
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling transistors beyond 20 nm due to physical, material, power-thermal, and economic limitations, leading to increased costs and decreased incentives for aggressive scaling, as well as issues with hardware security and intellectual property rights violations.
Innovation Solution
The development of Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and Microscale Modular Assembled ASIC (M2A2) technologies, which involve the use of prefabricated blocks (PFBs) assembled using nano-precise pick-and-place techniques, allowing for the creation of larger semiconductor devices with improved overlay precision and hardware security through split-fabrication approaches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor scaling continues beyond 20 nm, then device density increases, but manufacturing cost increases and production becomes economically unviable
Solution Approach 1:
The patent divides the semiconductor manufacturing process into multiple stages: initial high-resolution patterning of critical blocks, followed by lower-resolution patterning of remaining areas, and finally assembly of pre-fabricated modules. This segmentation allows expensive high-resolution processes to be applied only where necessary, reducing overall manufacturing costs while maintaining high device density through modular integration.
Solution Approach 2:
The patent transitions from conventional 2D planar scaling to 3D stacked architectures by assembling multiple layers of pre-fabricated blocks vertically. This dimensional change enables continued density improvement without requiring further reduction in lateral feature sizes, thereby avoiding the economic penalties of sub-20 nm patterning for all device components.
2Length of moving object
If sub-20 nm features are patterned using photolithography, then transistor size decreases, but process complexity increases requiring multiple patterning or EUV tools
Solution Approach 1:
The patent segments the patterning process into two distinct stages: first, high-resolution patterning is applied only to critical blocks requiring sub-20 nm features, while the remainder of the device is patterned using lower-resolution, simpler processes. This reduces overall process complexity by avoiding the need for multiple patterning cycles or EUV tools across the entire device.
Solution Approach 2:
The patent performs preliminary high-resolution patterning of critical blocks before assembling them into the final device structure. By preparing these high-precision components in advance as separate modules, the complex patterning process is isolated to specific regions rather than requiring complex multi-step patterning of the entire device.
3Device complexity
If monolithic construction is used for large semiconductor devices, then integration is simplified, but die size exceeds 900 mm2 causing manufacturing limitations
Solution Approach 1:
The patent divides large semiconductor devices into multiple smaller pre-fabricated blocks, each within the 900 mm2 manufacturing limit. These segmented blocks are then assembled into the final large-scale device, enabling production of devices exceeding 900 mm2 through modular integration rather than monolithic fabrication.
Solution Approach 2:
The patent resolves the die size limitation by transitioning from a single-plane monolithic structure to a three-dimensional stacked architecture. Multiple sub-900 mm2 blocks are arranged and connected across vertical layers, effectively creating large functional devices while maintaining each individual block within manufacturable size limits.
4Reliability
If split-fabrication is used for hardware security, then IP protection improves, but overlay precision between assembled blocks becomes challenging
Solution Approach 1:
The patent introduces specialized intermediary structures including alignment marks, registration features, and precision bonding interfaces that mediate between separately fabricated blocks. These intermediaries enable accurate overlay and registration of blocks from different fabrication sources, achieving the required precision despite the distributed manufacturing approach needed for hardware security.
Data Source
AI summary
Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.