3D IC Pick-and-Place Assembly for Sub-20 Nm Scaling
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Solution Overview
Problem
Conventional semiconductor manufacturing faces challenges in scaling beyond 20 nm features due to physical, material, power-thermal, and technological limitations, leading to increased production costs and decreased performance without commensurate gains, and there is a need for secure fabrication methods to protect intellectual property in the supply chain.
Innovation Solution
The use of nano-precise pick-and-place assembly techniques with prefabricated blocks (PFBs) and buried sacrificial layers, combined with moiré-based metrology and overlay correction, allows for the assembly of 3D stacked integrated circuits (N3-SI) and Microscale Modular Assembled ASICs (M2A2), enabling ultra-high density heterogenous integration and secure fabrication across trusted and untrusted foundries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used for patterning sub-20 nm features, then manufacturing process is simple, but manufacturing precision deteriorates due to physical and material limitations
Solution Approach 1:
The patent segments the monolithic fabrication process into multiple independent die fabrication steps followed by assembly. Each die can be fabricated separately using conventional photolithography, then assembled with sub-100 nm precision using specialized assembly tools. This segmentation allows each fabrication step to remain simple while achieving high overall precision through modular assembly.
Solution Approach 2:
The patent transitions from 2D planar integration to 3D stacked integration by assembling multiple tiers of dies vertically. This dimensional change enables continued scaling and density improvement without requiring further reduction in lateral feature sizes, thereby avoiding the physical limitations of sub-20 nm photolithography.
2Quantity of substance
If transistor size is reduced to increase density, then quantity of transistors increases, but power-thermal challenges worsen due to non-scaling supply voltage
Solution Approach 1:
The patent moves from 2D transistor scaling to 3D stacked integration, organizing transistors across multiple vertical tiers. This dimensional transition allows high transistor density to be achieved through vertical stacking rather than lateral compression, thereby maintaining better power-thermal characteristics as supply voltage does not scale proportionally with size reduction.
3Adaptability or versatility
If monolithic integration is used for system on chip, then functionality is integrated, but fabrication security worsens due to supply chain trust issues
Solution Approach 1:
The patent segments the system into multiple separate dies that can be fabricated in different locations using different fabrication processes. These segmented dies are then assembled together, allowing trusted and untrusted fabrication facilities to coexist in the supply chain while maintaining overall system functionality and security through controlled assembly.
Solution Approach 2:
The patent introduces a trusted assembly facility as an intermediary between untrusted fabrication sources and the final integrated system. This intermediary controls the assembly process, verifies die authenticity, and ensures secure integration, thereby resolving supply chain trust issues while maintaining functional integration.
4Manufacturing precision
If advanced patterning techniques are used for sub-20 nm features, then manufacturing precision improves, but production cost increases due to complex multiple-patterning
Solution Approach 1:
The patent segments the high-precision requirements into the assembly process rather than the fabrication process. Conventional photolithography can be used for die fabrication, while sub-100 nm precision is achieved during assembly using specialized alignment and placement tools. This segmentation maintains manufacturing simplicity while achieving high precision where it is most needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables nano-meter precise assembly of circuit elements, reduces overlay errors, and ensures hardware security by allowing partial fabrication at untrusted facilities, while maintaining lithographic precision and reducing production costs.
Implementation Method 1
a moiré-based metrology mechanism configured to sense overlay errors when assembling the one or more dies in the first substrate onto the second substrate
Data Source
AI summary
Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.