3D IC Vertical Interconnection via Planar Via Formation
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Solution Overview
Problem
The challenge in three-dimensional integrated circuit fabrication is the high cost and reduced yield due to the increased number of photolithography masking levels required for vertical interconnection, which limits the scaling of feature sizes and consumes significant silicon substrate, especially when forming electrical connections between stacked ICs.
Innovation Solution
A method that reduces the number of masking steps by forming vias and conductive material connections on a planar surface, allowing direct bonding of ICs with conductive material connections, thereby minimizing silicon consumption and optimizing interconnection density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional photolithography masking levels are used to form vertical interconnections, then electrical connections between stacked ICs can be achieved, but the number of masking steps increases, leading to reduced yield and increased cost
Solution Approach 1:
The method performs preliminary actions by forming conductive material connections and vias on a planar surface before stacking ICs. This preliminary preparation of interconnection structures eliminates the need for multiple post-stack photolithography masking steps, thereby reducing process complexity and improving yield.
Solution Approach 2:
The invention transitions from planar (2D) photolithography masking to three-dimensional (3D) direct bonding with pre-formed conductive connections. By forming interconnections in the vertical dimension before stacking, the method reduces the number of lateral masking steps required.
2Length of moving object
If multiple photolithography masking levels are used for vertical interconnection, then electrical connections can be formed, but feature size scaling is limited and silicon substrate is consumed
Solution Approach 1:
The method performs preliminary actions by forming conductive material connections and vias on a planar surface before stacking ICs. This preliminary preparation of interconnection structures eliminates the need for multiple post-stack photolithography masking steps, thereby reducing process complexity and improving yield.
Solution Approach 2:
The invention extracts the interconnection formation process from the conventional photolithography sequence and performs it separately on a planar surface before stacking. This separation removes the constraint of multiple masking levels and reduces silicon substrate consumption.
3Productivity
If direct bonding is used to vertically stack ICs, then interconnection density can be enhanced, but the complexity of forming conductive material connections must be reduced
Solution Approach 1:
The method performs preliminary actions by forming conductive material connections and vias on a planar surface before stacking ICs. This preliminary preparation of interconnection structures eliminates the need for multiple post-stack photolithography masking steps, thereby reducing process complexity and improving yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the complexity and cost of vertical interconnection, enhances interconnection density, and reduces silicon substrate consumption, improving the yield and scalability of three-dimensional integrated circuits.
Implementation Method 1
bonding the first element to the second element such that one of the first contact structure and the conductive material is directly connected to the second contact structure
Data Source
AI summary
A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.