3D Integrated Circuit Polysilicon Fin Formation for Higher Density
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing integration density due to physical constraints in two-dimensional IC formation, leading to the need for three-dimensional (3D) ICs to enhance component density and reduce complex designs.
Innovation Solution
A method for forming 3D ICs involves patterning a dielectric layer to create holes, depositing amorphous silicon, and crystallizing it into polysilicon, which is then patterned into silicon fins and used to form transistors, allowing for higher transistor density and reduced grain boundaries for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional IC formation is used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar transistor structures to three-dimensional vertically-oriented FinFET structures. The fins extend vertically from the substrate, creating a third dimension for current flow and significantly increasing the effective channel area without increasing the lateral footprint, thereby achieving higher integration density while maintaining manufacturing feasibility through adapted fabrication processes
2Quantity of substance
If more devices are integrated into one chip, then component density increases, but design complexity increases
Solution Approach 1:
The patent divides the chip into multiple distinct layers: substrate layer, fin structure layer, gate electrode layer, and interconnect layer. Each layer performs specific functions and can be independently optimized and manufactured, reducing overall design complexity while achieving high component density through vertical stacking
3Manufacturing precision
If minimum feature size is reduced, then 2D integration density improves, but physical limits are approached
Solution Approach 1:
Instead of continuing to reduce minimum lateral feature sizes, the patent introduces vertical fins that extend upward from the substrate. This transforms the scaling approach from lateral dimension reduction to vertical dimension exploitation, achieving higher integration density without approaching the physical limits of lithographic feature size reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of 3D ICs with increased transistor density and reduced leakage current, improving on-current performance and reducing the area required for PMOS power transistors, thus overcoming the limitations of 2D ICs.
Implementation Method 1
crystallizing it into polysilicon
Data Source
AI summary
A method includes following steps. An interconnect structure is formed over a first transistor. A dielectric layer is formed over the interconnect structure. The dielectric layer is etched to form holes in the dielectric layer. An amorphous layer is deposited in the holes of the dielectric layer and on a top surface of the dielectric layer. The amorphous layer is crystallized into a polycrystalline layer. A second transistor is formed on the polycrystalline layer.