3D IC Semiconductor Package Stacking for Higher POP Yield
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Solution Overview
Problem
Existing package-on-package (POP) technology requires discarding entire system-on-chip (SOC) when individual semiconductors are defective, leading to reduced yield and increased manufacturing costs, as it does not allow for the differentiation and stacking of individual semiconductors as 3D IC structures.
Innovation Solution
A semiconductor package and method that involves forming a 3D IC structure by stacking individual semiconductors on a front side redistribution layer using through-silicon vias and connection members, with an insulating member and molding material to encapsulate the chips, allowing for the implementation of SOC as 3D IC structures within the POP process, thereby reducing the need for separate 3D IC fabrication and minimizing epoxy molding compound usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If individual semiconductors are differentiated and stacked as 3D IC structures in the POP process, then manufacturing yield is improved and costs are reduced, but device complexity and fabrication process complexity increase
Solution Approach 1:
The system-on-chip is segmented into multiple individual semiconductor chips, each fabricated separately and then stacked vertically to form a 3D IC structure. This segmentation allows each chip to be independently tested and replaced if defective, eliminating the need to discard the entire SOC and thereby improving manufacturing yield.
Solution Approach 2:
The patent transitions from a traditional planar 2D SOC layout to a vertical 3D stacked architecture. Individual semiconductor chips are stacked in the vertical dimension, enabling better heat dissipation, reduced inter-chip connectivity complexity, and improved manufacturing yield through selective replacement of defective chips.
2Area of moving object
If 3D IC structures are fabricated separately before POP assembly, then integration density is improved, but manufacturing cost and process time increase due to separate fabrication
Solution Approach 1:
The patent merges the 3D IC structure fabrication process with the existing POP assembly process. Instead of fabricating 3D IC structures separately and then assembling them into POP packages, the individual semiconductors are differentiated and stacked directly within the POP fabrication flow, eliminating redundant process steps and reducing manufacturing cost.
3Ease of manufacture
If traditional POP technology is used without 3D IC structure integration, then fabrication process is simpler, but epoxy molding compound usage increases and yield is reduced
Solution Approach 1:
By transitioning to a 3D stacked architecture, the patent reduces the horizontal footprint of the package, thereby minimizing the amount of epoxy molding compound required for encapsulation. The vertical stacking allows more efficient use of package volume and reduces material consumption.
Data Source
AI summary
A semiconductor package includes: a front side redistribution layer; a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die having through-silicon vias (TSVs) and a second semiconductor chip die disposed on the first semiconductor chip die, and the second semiconductor chip die being electrically coupled with the front side redistribution layer by the through-silicon vias (TSVs); a plurality of connection members between the first semiconductor chip die and the second semiconductor chip die; an insulating member disposed between the first semiconductor chip die and the second semiconductor chip die to surround the plurality of connection members; a molding material disposed on the front side redistribution layer to encapsulate the first semiconductor chip die, the second semiconductor chip die, and the insulating member; and a back side redistribution layer disposed on the molding material.