3D IC Power Delivery Layout for Noise and Heat Transfer
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Solution Overview
Problem
As the level of integration in integrated circuit semiconductor devices increases, power delivery noise and heat transfer issues become significant challenges, affecting device reliability and performance.
Innovation Solution
The integrated circuit semiconductor device incorporates a substrate with a rail through via and a heat transfer through via, along with a cell-level portion, signal wiring-level portion, and power delivery network-level portion, which includes buried rails, local conductive interconnects, heat transfer lines, and multi-layer interconnect layers to reduce power delivery noise and enhance heat transfer characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the level of integration of integrated circuit semiconductor devices increases, then device functionality and density are improved, but power delivery noise increases and heat transfer becomes more difficult
Solution Approach 1:
The patent divides the semiconductor device into distinct functional levels: cell-level portion, signal wiring-level portion, and power delivery network-level portion. This segmentation separates signal wiring from power delivery networks, allowing independent optimization of each subsystem to reduce power delivery noise while maintaining high device density.
Solution Approach 2:
The patent introduces a vertical three-dimensional structure with multiple stacked levels for different functions. The cell-level portion, signal wiring-level portion, and power delivery network-level portion are arranged vertically, utilizing the third dimension to separate conflicting functions (signal routing and power delivery) that would interfere with each other in a planar layout, thereby reducing power delivery noise while achieving high integration density.
2Productivity
If the level of integration of integrated circuit semiconductor devices increases, then device functionality is improved, but heat generation increases and heat transfer becomes more difficult
Solution Approach 1:
The patent segments the device structure into distinct thermal management zones within each level. Heat transfer lines are separately provided in the cell-level portion and signal wiring-level portion, creating dedicated thermal pathways that can efficiently conduct heat away from high-density active regions without interfering with electrical signal routing.
Solution Approach 2:
The patent introduces heat transfer lines as intermediary thermal conduction pathways between the active device regions and heat dissipation structures. These heat transfer lines act as thermal mediators, efficiently conducting heat away from the high-density cell-level and signal wiring-level portions through dedicated thermal pathways, preventing heat accumulation while maintaining high integration.
3Device complexity
If signal wiring and power delivery networks are integrated in the same plane, then device complexity is reduced, but power delivery noise increases
Solution Approach 1:
The patent transitions from a two-dimensional planar integration to a three-dimensional stacked architecture. Signal wiring is placed in the signal wiring-level portion while power delivery networks are positioned in the power delivery network-level portion at different vertical levels. This spatial separation in the third dimension effectively reduces electromagnetic interference and power delivery noise while maintaining relatively simple device structure through standardized multi-layer fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces power delivery noise and improves heat transfer characteristics, leading to enhanced device reliability and performance by separating signal wiring and power delivery networks and utilizing dedicated heat transfer paths.
Implementation Method 1
a heat transfer line connected to the upper multi-layer interconnect layer and formed in the cell-level portion and the signal wiring-level portion
Implementation Method 2
a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate
Data Source
AI summary
An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.