3D IC Power Grid Ladder Structure for Low-IR-Drop Stacking
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Solution Overview
Problem
3D IC power grid designs face challenges such as large IR drop and inductive voltage fluctuations due to the use of Through-Silicon Vias (TSVs) in power distribution networks, which are not suitable for Face-to-Face die stacking, and conventional 2D power grids are inadequate for these designs.
Innovation Solution
A power distribution structure combining short TSVs, a grid ladder, and power grid bones is used to distribute power from top metals to device layers through a traditional 2D power grid structure, minimizing IR drop by direct coupling of the power supply from packaging bumps to interface top metals, and extending this solution to multiple stacked dies to replace long TSV structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If Through-Silicon Vias (TSVs) are used in power distribution networks for 3D IC, then vertical interconnection is achieved, but large IR drop and inductive voltage fluctuations occur
Solution Approach 1:
The power distribution network is segmented into multiple hierarchical levels: top metal layer, intermediate TSVs, ladder network stages, and 2D power grids at each die level. This segmentation divides the long vertical TSV path into shorter segments with intermediate power distribution points, reducing the effective resistance and inductance of any single path and thereby minimizing IR drop and voltage fluctuations.
Solution Approach 2:
The invention transitions from a purely vertical 3D power distribution approach to a hybrid architecture that incorporates 2D power grid planes at intermediate levels. By adding this intermediate dimensional layer (the 2D power grids embedded in through-silicon interconnect layers), power can be distributed both vertically through TSVs and laterally through metal traces, reducing dependence on long vertical paths and minimizing IR drop.
2Device complexity
If conventional 2D power grids are used, then simple structure is maintained, but they are inadequate for 3D IC power distribution
Solution Approach 1:
The power distribution architecture employs a nested structure where 2D power grids are embedded within through-silicon interconnect layers, which are themselves nested within the 3D stacked die configuration. Each die contains a 2D power grid that is nested in its substrate, and these are vertically nested through TSVs connecting to ladder networks, creating a multi-level nested power distribution system that maintains structural simplicity while achieving 3D power distribution adequacy.
3Length of moving object
If long TSV structures are used for power distribution, then vertical power delivery is achieved, but inductive voltage fluctuations increase
Solution Approach 1:
The long TSV structure is segmented into multiple shorter TSVs arranged in stages within the ladder network. Instead of one long TSV carrying all current, multiple shorter TSVs distribute current in parallel at different vertical levels. This segmentation reduces the effective inductance of each TSV segment and provides multiple parallel current paths, thereby reducing inductive voltage fluctuations (L di/dt noise).
Solution Approach 2:
Ladder network structures act as intermediary elements between the top metal power input and the device layers. These ladder networks provide intermediate coupling points that mediate the power transfer, reducing the direct inductive coupling effect of long TSVs by introducing distributed RC elements that filter high-frequency noise and reduce inductive voltage fluctuations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces IR drop and achieves similar supply voltages across multiple stacked dies, improving power distribution efficiency in 3D IC designs by using a combination of short TSVs, ladder networks, and 2D power grids, addressing the limitations of conventional 3D power grid processes.
Implementation Method 1
A vertically stacked integrated circuit may stack semiconductor dies on top of each other and may interconnect the semiconductor dies vertically using, for example, Through-Silicon Vias (TSVs)
Implementation Method 2
A voltage loss may occur based at least in part on a resistance associated with a conductive path that a signal may travel from the power supply to the circuit
Data Source
AI summary
A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.