3D IC Stack Layout With Rotated Chips for Fewer Pads and TSVs
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Solution Overview
Problem
The integration of multiple chips in 3D integrated circuits (ICs) faces challenges in distributing power and signals efficiently, leading to increased system design complexity and potential signal propagation issues, particularly in scalable systems like neural recording systems, CMOS image sensors, and touch sensors.
Innovation Solution
The proposed IC system employs a stacked configuration with a first substrate and power managing IC chips, control IC chips, and second power managing IC chips, where IC chips are rotated and flipped to minimize the number of pads and through-silicon vias (TSVs) required for power and signal transmission, allowing for efficient power distribution and signal propagation with a minimal number of interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are integrated in 3D ICs with conventional stacking, then functionality and integration are improved, but system design complexity and signal propagation issues increase
Solution Approach 1:
The patent applies asymmetry by rotating IC chips at different angles (e.g., 0°, 90°, 180°, 270°) relative to each other in the stacked configuration. This asymmetric arrangement allows power and signal pads to be distributed more efficiently across the stacking interface, reducing the concentration of interconnects in specific areas and thereby simplifying the overall system design while maintaining high integration functionality.
Solution Approach 2:
The patent transitions from conventional 2D pad layout to 3D spatial arrangement by stacking IC chips vertically with rotational offsets. This dimensional change allows power and signal transmission to occur through multiple vertical layers with distributed pad locations, reducing the number of pads required at any single interface and simplifying the design complexity of the interconnect structure.
2Reliability
If more pads and TSVs are used for power and signal transmission, then power distribution and signal propagation are improved, but heat increase and power consumption increase
Solution Approach 1:
The patent segments the power and signal transmission paths by distributing pads across multiple rotated IC chips in the stack. Instead of concentrating all power and signal pads in a single layer, the segmentation approach spreads them across multiple vertical levels, allowing shorter and more efficient transmission paths that reduce power consumption while maintaining reliable signal propagation.
Solution Approach 2:
The patent utilizes the vertical dimension in 3D stacking to create multiple pathways for power and signal transmission. By arranging pads at different vertical levels and rotational angles, the system achieves redundant transmission paths that improve reliability without requiring an excessive number of pads, thereby reducing overall power consumption compared to conventional 2D layouts.
3Ease of manufacture
If conventional IC stacking is used, then manufacturing is simplified, but heat dissipation and voltage accuracy deteriorate
Solution Approach 1:
The patent employs asymmetric rotational stacking of IC chips to create spatial separation between power-consuming components and heat-generating elements. This asymmetric arrangement improves heat dissipation by distributing thermal sources across different vertical and angular positions, preventing heat concentration while maintaining manufacturing feasibility through standardized bonding processes.
Solution Approach 2:
The patent segments the thermal management approach by distributing power pads and signal pads across multiple rotated chips rather than concentrating them in one location. This segmentation reduces localized heat generation and improves overall heat dissipation efficiency, while the modular stacked structure remains compatible with existing manufacturing techniques.
4Ease of manufacture
If IC chips are arranged without rotation, then alignment and manufacturing are simplified, but the number of pads and TSVs required increases
Solution Approach 1:
The patent introduces controlled asymmetric rotations (e.g., 0°, 90°, 180°, 270°) of IC chips in the stack. This asymmetric arrangement allows power and signal pads to be positioned at optimal locations on each chip, enabling shared use of pads across multiple chips through the rotational geometry. Consequently, the total number of pads required is reduced compared to conventional non-rotated stacking, while alignment remains feasible through precise rotational positioning.
Data Source
AI summary
An integrated circuit (IC) system including a first substrate comprising passive components, a first power managing IC chip including a first power managing IC stacked on the first substrate, first IC chip group including a IC stacked on top of the first power managing IC chip, a control IC chip, stacked on top of the first IC group, including a control IC configured to control the first IC and a second IC of a second IC chip group, the second IC chip group including the second IC stacked on top of the control IC chip, a second power managing IC chip including a second power managing IC stacked on top of the second IC chip group, and a second substrate comprising passive components stacked on top of the second power managing IC chip.