3D IC Seal Ring Venting for Hybrid Bonding Reliability

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Solution Overview

Problem

The semiconductor industry faces challenges in further shrinking minimum feature sizes on integrated circuits due to process limitations, leading to difficulties in improving processing capabilities and power consumption, which is addressed by stacking two-dimensional ICs into three-dimensional ICs with a seal ring structure that traps gas, causing reliability concerns and pressure issues during bonding.

Innovation Solution

A seal ring structure with a sidewall gas-venting structure is introduced, featuring openings that allow gas to escape and promote strong hybrid bonding between stacked IC dies, while ensuring electrical connection and protection from environmental factors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a seal ring structure is used to enclose contact pads during 3D IC bonding, then environmental protection and electrical isolation are improved, but gas trapping and pressure buildup occur causing bonding reliability to deteriorate

Engineering Contradiction:
Improveenvironmental protectionVSAvoidbonding reliability
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The seal ring is segmented into discrete blocks rather than forming a continuous structure. These segmented seal ring blocks are positioned around the contact pads, providing environmental protection and electrical isolation while creating gaps that allow gas to escape during bonding, thus preventing pressure buildup and improving bonding reliability.

Inventive Principle:
Principle #1Segmentation

2Productivity

If minimum feature size is shrunk to improve processing capabilities, then device density increases, but process limitations make further shrinking difficult

Engineering Contradiction:
Improveprocessing capabilitiesVSAvoidprocess limitations
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional IC scaling to three-dimensional IC stacking. By stacking multiple IC layers vertically, the patent achieves continued improvement in processing capabilities and device density without further shrinking the minimum feature size in the planar dimension, thereby overcoming process limitations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If hybrid bonding is performed between stacked IC dies, then electrical connection is achieved, but trapped gas causes pressure issues that weaken bonding strength

Engineering Contradiction:
Improveelectrical connectionVSAvoidbonding strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The seal ring is divided into segmented blocks with gaps between them, allowing trapped gas to escape during hybrid bonding while maintaining electrical connection between IC dies. This segmentation prevents pressure buildup that would otherwise weaken bonding strength.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent converts the potentially harmful effect of trapped gas during bonding into a beneficial outcome by designing the segmented seal ring to deliberately allow gas escape. The gaps between seal ring blocks serve as venting pathways, transforming the gas trapping problem into a controlled gas release mechanism that actually improves bonding quality.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11842992B2Seal ring structures and methods of forming same
Publication Date: 2023.12.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11842992B2 patent drawing
  • US11842992B2 patent drawing
  • US11842992B2 patent drawing

AI summary

Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.