3D IC Security Layer Obfuscation via Segmentation

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Solution Overview

Problem

Current methods for manufacturing integrated circuits lack effective security measures to prevent counterfeiting and reverse engineering, particularly in 3D ICs, where outsourcing fabrication processes can expose chip designs to unauthorized access and Trojan circuit implantation.

Innovation Solution

A method is introduced that adds a security layer between neighboring layers of the 3D IC, utilizing programmable logic arrays and floating gate MOSFETs with non-volatile memory to obfuscate critical logic blocks and interconnects, making it difficult for adversaries to extract chip functionality even through intense reverse engineering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a security layer is added between neighboring layers of the 3D IC, then security against reverse engineering is improved, but device complexity increases

Engineering Contradiction:
ImprovesecurityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The 3D IC is divided into multiple tiers with a dedicated security layer inserted between functional layers. This segmentation isolates critical logic blocks and interconnects within the security layer, preventing adversaries from extracting chip functionality even when accessing other layers. The security layer acts as a barrier that segments the chip into protected and unprotected zones.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The security layer serves as an intermediary between functional layers, containing programmable logic arrays and floating gate MOSFETs that mediate access to critical circuits. This intermediary structure obfuscates the connection between input and output, making reverse engineering difficult while allowing legitimate functionality to pass through.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If outsourcing fabrication processes is implemented, then manufacturing cost and time are improved, but security against unauthorized access deteriorates

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidsecurity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The chip fabrication is segmented into multiple tiers that can be manufactured by different foundries. The security layer containing critical logic blocks is manufactured separately and then bonded between functional layers. This segmentation allows outsourcing of non-critical layers while protecting intellectual property in the security layer, even when final bonding is outsourced.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The security layer is prepared in advance with obfuscated critical logic blocks before final assembly. By preliminarily configuring the security layer with protected circuits and programmable logic arrays, the design ensures that even if outsourcing is used for final bonding, the critical functionality remains secured through pre-established protective measures.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If programmable logic arrays and floating gate MOSFETs are used to obfuscate critical logic blocks, then security is improved, but manufacturing precision requirements increase

Engineering Contradiction:
ImprovesecurityVSAvoidmanufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The security layer utilizes programmable logic arrays and floating gate MOSFETs that can be configured after manufacturing through voltage application. This parameter change capability allows the same physical structure to serve multiple functions and provides post-fabrication security configuration, reducing the need for extremely tight manufacturing tolerances while maintaining security.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the security of 3D ICs by preventing reverse engineering and counterfeiting, ensuring that critical logic blocks and interconnects remain protected, even when the final bonding of tiers is outsourced, thereby safeguarding against Trojan circuits and unauthorized access.

Implementation Method 1

floating gate MOSFETs with non-volatile memory to obfuscate critical logic blocks

Methodology Applied
Scientific EffectNon-volatile memory storage:

Implementation Method 2

a deep ion implanted layer of degenerated states is added to the FG transistor below the surface

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS11392746B2Method for the non-copyable manufacture of integrated circuits
Publication Date: 2022.07.19 UNIVERSITY OF LOUISIANA AT LAFAYETTE
  • US11392746B2 patent drawing
  • US11392746B2 patent drawing
  • US11392746B2 patent drawing

AI summary

The method for creating integrated circuits (IC) protects the design of a manufactured IC from being copied or counterfeited. This method protects the design of an IC chip from deliberate copying and counterfeiting by reverse engineering to gain access to the critical points in the IC chip and to siphon its functions and design. The method makes the copying, counterfeiting, and controlling by addition of Trojan circuits during manufacturing almost impossible task. It also allows chip designers to outsource the final bonding of the tiers without any fears that their design may get compromised.