3D IC Device With Self-Aligned Transistors
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Solution Overview
Problem
Current 3D stacked integrated circuits face challenges in connecting embedded memories with logic transistors due to temperature compatibility issues and limited connectivity, leading to inefficient use of chip area and increased costs.
Innovation Solution
The development of 3D IC devices with self-aligned junction-less transistors and shared lithography steps allows for the construction of multilayer stacks with improved connectivity and optimized transistor design, enabling efficient integration of memory and logic layers without exposing them to high temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are constructed in 3 dimensions above wiring layers at high temperatures (>700°C), then transistor performance is improved, but the bottom wiring layer is damaged
Solution Approach 1:
The patent divides the transistor structure into multiple layers: bottom transistors on the first substrate, middle wiring layers, and top transistors on a second substrate. This segmentation allows each layer to be optimized independently and prevents high-temperature processing from damaging the wiring layer, as the top transistors are formed on a separate substrate that can withstand the temperature.
Solution Approach 2:
The patent implements a nested structure where the top transistor layer is stacked above the bottom transistor layer with wiring layers in between. The top transistors are effectively nested within the vertical space above the bottom transistors, allowing both layers to coexist without thermal interference while maintaining electrical connectivity through through-silicon vias.
2Ease of operation
If Through-Silicon Via (TSV) contacts are used to connect stacked wafers, then vertical connectivity is achieved, but contact size must be large and contact density is limited
Solution Approach 1:
The patent transitions from 2D planar contacts to 3D vertically stacked contacts. By utilizing the vertical dimension, multiple contact points can be established between stacked wafers without increasing the lateral footprint. This allows high contact density while maintaining manageable contact sizes, as contacts are distributed across multiple vertical levels rather than competing for the same planar space.
3Area of stationary object
If embedded memories are placed in separate device layers from logic transistors, then area overhead is reduced, but temperature compatibility and integration complexity increase
Solution Approach 1:
The patent segments the integrated circuit into distinct functional layers: logic transistor layers and memory transistor layers, stacked vertically. This allows each layer type to be optimized for its specific function while sharing common wiring infrastructure. The segmentation reduces area overhead by utilizing the vertical dimension for memory expansion without increasing the lateral chip footprint.
Solution Approach 2:
The patent creates a universal stacked architecture that can accommodate both logic and memory transistors in the same vertical stack. The common wiring layers and shared substrate structure provide multi-functionality, allowing the same physical infrastructure to support different transistor types and functions, thereby reducing integration complexity despite the vertical separation of functions.
Data Source
AI summary
A 3D device, including: a first layer including a first memory including a first transistor; a second layer including a second memory including a second transistor; and a Resistive RAM structure, where the second transistor is self-aligned to the first transistor, and where the Resistive RAM structure is overlaying the first layer and is overlaid by the second layer.