3D IC Serial Gate MOS Devices via TSV Interconnects
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Solution Overview
Problem
In advanced semiconductor processes, the reduction in gate length of MOS devices increases mismatch and affects the source-to-drain resistance (Rout) in analog circuits, necessitating a solution to maintain performance without increasing chip area.
Innovation Solution
Implementing a series MOS technique by connecting multiple transistors in series across stacked dies in a 3D IC configuration, where each transistor has a shorter gate length, and using through-substrate vias to connect gate electrodes and source/drain regions across dies, effectively maintaining the total resistance and reducing the horizontal dimension of the serial gate MOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If gate length is reduced in advanced semiconductor processes, then device size is reduced, but mismatch increases and Rout is affected
Solution Approach 1:
The patent divides a single long gate-length transistor into multiple shorter gate-length transistors connected in series. Each transistor in the series has a reduced gate length suitable for advanced semiconductor processes, while the series connection maintains the total gate length equivalent to the original single transistor, thereby preserving analog performance (Rout and mismatch characteristics) while enabling fabrication in advanced nodes with shorter minimum gate lengths.
Solution Approach 2:
The patent extends the transistor chain into the vertical dimension by stacking multiple dies in a 3D integrated circuit configuration. Through-substrate vias connect transistors on different dies in series, allowing the analog circuit to achieve the required total gate length by distributing transistors across multiple vertical layers rather than extending horizontally, thus reducing chip area while maintaining performance.
2Reliability
If multiple transistors are connected in series to maintain Rout, then analog performance is maintained, but horizontal length increases
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked configuration. Multiple transistors are distributed across vertically stacked dies and connected in series through through-substrate vias. This vertical stacking approach achieves the required total gate length for maintaining analog performance (Rout) without proportionally increasing the horizontal chip footprint, as the length extension occurs primarily in the vertical dimension rather than horizontally.
3Area of moving object
If gate length is reduced for scaling, then chip area is reduced, but mismatch increases
Solution Approach 1:
The patent segments the analog circuit function across multiple shorter transistors in series, each with gate lengths optimized for advanced semiconductor processes. The series connection of these segmented transistors maintains the total gate length required for low mismatch and high Rout, while individual transistor dimensions are scaled down to take advantage of advanced process node benefits including reduced chip area.
Data Source
AI summary
A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.