3D IC Serial Gate MOS Device via TSV Interconnects

The patent divides a single long gate transistor into multiple shorter gate length transistors connected in series. Each transistor in the series has a reduced gate length (e.g., L/3) compared to the original single transistor (L), allowing the use of advanced process nodes while maintaining the equivalent total gate length and thus preserving analog performance characteristics like mismatch and source-to-drain resistance.

The patent extends the transistor series connection into the vertical dimension by stacking multiple dies in a 3D integrated circuit configuration. Through-substrate vias (TSVs) are used to connect the source of one transistor to the drain of another across different dies, enabling the series connection to span multiple vertical layers and further reducing the horizontal footprint while maintaining the required total gate length.

The patent transitions from a planar 2D layout to a 3D stacked configuration using multiple dies connected via through-substrate vias. This vertical stacking allows multiple transistors to be connected in series without proportionally increasing the horizontal chip area, as the series connection extends into the vertical dimension rather than requiring additional horizontal space.

The patent implements a nested structure where multiple transistor devices are stacked vertically within a compact footprint. Each die contains transistors that are physically nested above or below other dies through TSV connections, creating a space-efficient configuration where the series-connected transistors occupy overlapping vertical space rather than requiring sequential horizontal placement.