3D IC Stacked Memory with Self-Aligned Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D stacked semiconductor chip technologies face challenges in achieving high-density connections between layers due to misalignment issues and temperature constraints that damage wiring layers, limiting connectivity and performance.
Innovation Solution
The development of multilayer 3D IC devices with self-aligned transistors and memory cells processed using lithography steps that allow for high-density connectivity, utilizing techniques such as ion-cut layer transfer and shared masks to construct horizontally-oriented transistors and memory cells with monocrystalline silicon layers, enabling efficient 3D integration without degrading existing layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are constructed at high temperatures (>700°C) to improve transistor performance, then transistor density and performance improve, but wiring layers are damaged due to exposure to temperatures higher than 400°C
Solution Approach 1:
The patent divides the 3D stacked structure into separate modules: bottom transistor layer, bottom wiring layer, top transistor layer, and top wiring layer. Each layer is constructed independently and then bonded together, allowing different processing temperatures for each module. This segmentation enables high-temperature transistor fabrication without exposing the wiring layers to damaging temperatures.
Solution Approach 2:
The wiring layers are constructed at low temperatures (below 400°C) before the transistor layers are formed at high temperatures. This preliminary action ensures that the temperature-sensitive wiring layers are already in place and protected before the high-temperature transistor fabrication process begins, preventing thermal damage to the interconnects.
2Adaptability or versatility
If Through-Silicon Via (TSV) contacts are used to connect stacked wafers, then 3D integration is achieved, but contact density is limited due to large landing pad sizes required for alignment
Solution Approach 1:
The patent transitions from vertical TSV contacts to horizontally-oriented transistors and memory cells. This dimensional change allows connections to be made in the lateral direction rather than requiring deep vertical vias, thereby increasing contact density without being constrained by alignment precision in the vertical stacking direction.
Solution Approach 2:
Instead of forming vertical contacts through thick silicon substrates (TSV approach), the patent inverts the approach by creating horizontally-oriented devices that connect laterally. This inversion eliminates the need for deep etching and filling operations, allowing for much higher density connections with relaxed alignment requirements.
3Manufacturing precision
If misalignment between bonded wafers is accommodated by increasing landing pad size, then alignment tolerance is improved, but contact density decreases
Solution Approach 1:
The patent changes the orientation of transistors and memory cells from vertical to horizontal, allowing connections to be established in the lateral dimension. This dimensional shift enables high-density interconnects without requiring large vertical landing pads, as the connections are made side-by-side rather than top-to-bottom through alignment-critical interfaces.
Data Source
AI summary
A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the second transistors; and fourth transistors, overlaying the third transistors, where the second transistors, the third transistors and the fourth transistors are self-aligned, being processed following the same lithography step, and where at least one of the first transistors is part of a control circuit controlling at least one of the second transistors, at least one of the third transistors and at least one of the fourth transistors.