3D IC Stacked Packages Reducing Interconnection Lengths
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Solution Overview
Problem
Two-dimensional integrated circuit technologies face limitations in increasing density and complexity due to physical constraints, such as minimum feature size and increased interconnections, leading to higher circuit RC delay and power consumption.
Innovation Solution
The implementation of three-dimensional integrated circuits (3D ICs) using wafer-on-wafer, die-on-wafer, and die-on-die technologies, where multiple wafers or dies are stacked and bonded with aligned devices, allowing for higher device density and reduced interconnection lengths through the use of via structures and redistribution layers within a molding compound.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more devices are integrated into one chip to increase density, then device density improves, but circuit RC delay and power consumption increase due to increased interconnections
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional stacked integration. Multiple semiconductor wafers are bonded together in a vertical stack, with through-silicon vias providing electrical interconnections between layers. This vertical stacking enables higher device density while keeping interconnection lengths short, thereby reducing power consumption and RC delay compared to continued 2D scaling.
2Quantity of substance
If more devices are integrated into one chip to increase density, then device density improves, but circuit RC delay increases due to increased interconnection length
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional stacked integration. Multiple semiconductor wafers are bonded together in a vertical stack, with through-silicon vias providing electrical interconnections between layers. This vertical stacking enables higher device density while keeping interconnection lengths short, thereby reducing power consumption and RC delay compared to continued 2D scaling.
3Quantity of substance
If two-dimensional integration continues to increase density, then more components fit in given area, but physical limits are reached due to minimum feature size constraints
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional stacked integration. Multiple semiconductor wafers are bonded together in a vertical stack, with through-silicon vias providing electrical interconnections between layers. This vertical stacking enables higher device density while keeping interconnection lengths short, thereby reducing power consumption and RC delay compared to continued 2D scaling.
4Quantity of substance
If wafer-on-wafer 3D IC technology is used to achieve higher device density, then integration density improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated circuit into multiple separate semiconductor wafers that are processed independently and then bonded together in a vertical stack. Each wafer can be manufactured using standard 2D IC processes, and the through-silicon vias provide vertical interconnections between layers. This segmentation approach enables higher device density while managing manufacturing complexity by allowing independent processing of each layer.
Data Source
AI summary
Packages and methods of manufacture thereof are described. In an embodiment, a package may include a first chip package and a die structure disposed over the first chip package. In an embodiment, the first chip package may include: a molding compound; a first die within the molding compound; a first via structure and a second via structure within the molding compound at opposite lateral portions of the first die, wherein the first and second via structures extend between an active surface of the first die and a first surface of the molding compound; and a second die within the molding compound, the second die disposed at the active surface of the first die and between the first via structure and the second via structure.