3D IC Stacked Tiers with Inter-Tier Vias for High I/O Density
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Solution Overview
Problem
Conventional 2D wiring in integrated circuit chips faces limitations such as high power consumption, I/O interconnect density limitations, and increased costs, particularly at advanced technology nodes like the 20 nanometer scale, which hinder system integration and yield in devices like FPGAs and GPUs.
Innovation Solution
The implementation of 3D IC package technology involving stacked functional tiers with inter-tier through vias (ITVs) and redistribution layers (RDLs) for electrical interconnections, allowing for higher I/O density and lower power consumption, and enabling heterogeneous or homogeneous stacking of logic, memory, and other functionalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional 2D wiring is used for interconnecting integrated circuit chips, then the wiring structure is simple and easy to manufacture, but the I/O interconnect density is limited and power consumption is high
Solution Approach 1:
The patent transitions from conventional 2D wiring to 3D wiring architecture, stacking multiple functional tiers vertically to achieve higher I/O interconnect density. The 3D interconnect structure includes through-silicon vias (TSVs) and redistribution layers (RDLs) that enable vertical signal routing, dramatically increasing the number of I/O connections per unit area compared to planar 2D wiring.
Solution Approach 2:
The integrated circuit is divided into multiple functional tiers (logic tier, memory tier, I/O tier) that are stacked and interconnected. Each tier contains specific functional blocks that are independently designed and then combined through 3D integration, allowing for modular manufacturing and optimized interconnect routing between tiers.
2Ease of manufacture
If conventional 2D wiring is used for interconnecting integrated circuit chips, then the manufacturing process is simpler, but power consumption and current leakage are high
Solution Approach 1:
By implementing 3D vertical interconnects with TSVs and RDLs, the patent reduces the average wire length for signal transmission compared to 2D routing. Shorter interconnect paths reduce resistive losses and dynamic power consumption, while the vertical stacking enables more compact device layouts that reduce overall system power requirements.
3Device complexity
If conventional 2D wiring is used, then the design is simpler, but the cost is high and yield is low, particularly at advanced technology nodes
Solution Approach 1:
The patent divides the integrated circuit into multiple functional tiers that can be manufactured separately using standard CMOS processes at advanced technology nodes, then combined through 3D integration. This segmentation allows for specialized optimization of each tier (logic, memory, I/O) and improves overall manufacturing yield by isolating process variations to individual tiers rather than affecting the entire chip.
Solution Approach 2:
The patent introduces intermediary structures (TSVs, RDLs, and bonding interfaces) that facilitate the connection between separately manufactured functional tiers. These intermediary elements serve as buffers that absorb manufacturing variations and enable high-yield production at advanced technology nodes by decoupling the fabrication processes of different functional blocks.
4Quantity of substance
If silicon interposer packages are used for 3D interconnection, then I/O connections are improved, but the package size and profile are increased
Solution Approach 1:
The patent employs vertical stacking of functional tiers connected by TSVs and RDLs, transitioning from horizontal 2D expansion to vertical 3D integration. This dimensional change enables high I/O connection capacity to be achieved within a compact footprint by utilizing the vertical dimension for signal routing, thereby reducing the required package area while maintaining or increasing I/O density.
5Productivity
If through silicon vias (TSVs) are used for 3D packaging, then packaging efficiency is improved, but power consumption is increased
Solution Approach 1:
The patent uses TSVs to create vertical interconnect pathways that significantly reduce the length of electrical signals compared to lateral routing in 2D packages. This vertical routing through the silicon substrate reduces resistive losses and enables more efficient power delivery, actually decreasing overall power consumption while improving packaging efficiency and enabling higher system integration.
Data Source
AI summary
An embodiment device package includes a fan-out redistribution layer (RDL), a device over and bonded to the fan-out RDL, and a molding compound over the fan-out RDL and extending along sidewalls of the device. The device includes a first functional tier having a first metallization layer and a second functional tier having a second metallization layer. The second functional tier is bonded to the first functional tier. The device further includes an interconnect structure electrically connecting the first metallization layer to the second metallization layer. The interconnect structure includes an inter-tier via (ITV) at least partially disposed in both the first functional tier and the second functional tier, and the ITV contacts the first metallization layer.