3D IC Stacked Transistors With TSV Interconnects
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Solution Overview
Problem
The development of true three-dimensional integrated circuits (3D ICs) faces challenges in yield and reliability due to the complexity of deep submicron process generations, particularly in Application Specific Integrated Circuits (ASICs), and existing testing techniques are not adequately adapted for these complex systems.
Innovation Solution
The implementation of a 3D device architecture with aligned transistors and clock distribution structures, utilizing Phase Lock Loop (PLL) circuits and Through Silicon Vias (TSVs) for interlayer connections, along with a programmable interconnect fabric using antifuse technology, allows for precise alignment and efficient testing, enhancing yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through Silicon Vias are constructed continuing vertically through all the layers creating a global interlayer connection, then interlayer connectivity is improved, but manufacturing complexity and alignment precision requirements increase
Solution Approach 1:
The patent segments the monolithic 3D IC into multiple separate 2D IC layers that are individually fabricated and then stacked vertically. Through-Silicon Vias (TSVs) are used to create interlayer connections between these stacked layers, allowing global connectivity without requiring complex through-layer via formation in a single monolithic substrate. This segmentation approach improves yield and reliability by enabling separate fabrication and testing of each layer.
Solution Approach 2:
The patent transitions from planar 2D IC interconnection to three-dimensional vertical stacking with TSVs providing through-layer connectivity. By adding the vertical dimension with stacked layers and TSVs, the system achieves global interlayer connection while maintaining manufacturing feasibility through separate layer fabrication followed by vertical assembly.
2Adaptability or versatility
If multiple layers of silicon are bonded together with Through Silicon Via technology to form a true 3D IC, then device functionality is improved, but yield and reliability difficulties increase due to complexity
Solution Approach 1:
The patent divides the complex 3D IC system into multiple independent 2D IC layers that can be fabricated, tested, and characterized separately before final assembly. This segmentation allows for better yield management and reliability assessment at each stage, reducing the compounding complexity issues that would arise from attempting to fabricate and test the entire monolithic 3D structure in one process.
Solution Approach 2:
The patent implements preliminary fabrication, testing, and characterization of each 2D IC layer before stacking and bonding. This preliminary action allows for defect detection and correction at the individual layer level, improving overall yield and reliability before the layers are permanently bonded together with TSVs to form the complete 3D IC system.
3Productivity
If standard two dimensional integrated circuits are stacked vertically in the same package, then integration density is improved, but true 3D IC functionality is not achieved
Solution Approach 1:
The patent implements true three-dimensional integration by stacking multiple 2D IC layers vertically and connecting them through Through-Silicon Vias that penetrate the entire thickness of each layer. This vertical stacking with through-layer connectivity transforms the system from planar 2D arrangement to genuine 3D architecture, enabling complex interlayer routing and global connectivity that cannot be achieved with simple vertical stacking alone.
Data Source
AI summary
A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the device includes a Phase Lock Loop (“PLL”) circuit, where the second clock distribution structure is connected to the Phase Lock Loop (“PLL”) circuit, and where the second transistors are aligned to the first transistors with less than 200 nm alignment error.