3D Single-Crystal IC Stacking for Dense Interlayer Connections
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the ability to produce a commercially viable range of products with different logic families, and existing 3D IC technologies are constrained by large Through-Silicon-Vias (TSVs) that restrict the number of connections that can be made.
Innovation Solution
The development of a 3D IC device fabrication method using a programmable antifuse structure with Through-Silicon-Via (TSV) technology, enabling the construction of configurable logic devices with multiple layers of antifuses for interconnection, and employing layer transfer techniques to achieve precise alignment and bonding of single crystal silicon layers, allowing for dense and small-sized connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional Through-Silicon-Via (TSV) technology is used for 3D IC interconnection, then vertical connections between layers are established, but the large size of TSVs restricts the number of connections that can be made
Solution Approach 1:
The patent transitions from traditional vertical TSV interconnection to a planar interconnection architecture where metal interconnect layers extend laterally across the substrate. This dimensional shift allows multiple signal paths to be established without requiring numerous vertical penetrations through the substrate, thereby increasing connection density while reducing the effective size of interconnection structures.
Solution Approach 2:
The patent divides the interconnection function into separate metal interconnect layers that are distributed across the substrate surface, rather than concentrating all connections through central TSV structures. This segmentation allows parallel interconnection paths to be established independently, increasing the total number of connections possible within the device footprint.
2Manufacturing precision
If multiple mask sets are used for semiconductor fabrication, then precise patterning is achieved, but manufacturing costs increase
Solution Approach 1:
The patent employs a single mask set that serves multiple patterning functions through self-aligned fabrication steps. The same mask structure is used to define both the metal interconnect regions and the transistor active areas in a self-aligned manner, eliminating the need for separate mask sets for different patterning operations and thereby reducing manufacturing costs while maintaining precision.
Solution Approach 2:
The fabrication process utilizes self-aligned patterning where previously deposited structures automatically serve as alignment references for subsequent deposition steps. This self-alignment mechanism eliminates the need for additional mask alignment steps, reducing both the number of mask sets required and the associated manufacturing costs while preserving patterning precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by minimizing the need for multiple mask sets and enables a high-density of connections in 3D ICs, enhancing the flexibility to produce various logic, memory, and analog functions within a single device, while overcoming the limitations of traditional TSV technology.
Implementation Method 1
the bonded includes oxide to oxide bonds
Implementation Method 2
the bonded includes metal to metal bonds
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where a top surface of the first level includes a first oxide region and a bottom surface of the second level includes a second oxide region, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, and where the second transistors are raised source drain extension transistors.