3D IC Substrate Flatness via Wafer Backside Preparation
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Solution Overview
Problem
Current methods for three-dimensional integrated circuit (IC) integration face challenges such as misalignment, thermal budget violations, and sensitivity to topographical variations, which affect the precision and reliability of interconnects and the flatness of semiconductor substrates, leading to increased manufacturing costs and performance issues.
Innovation Solution
A method and system that analyze and modify insulating dielectric layers and semiconductor substrates to ensure they meet the requirements for flatness and smoothness, using concurrent models to determine necessary parameters and processes for depositing and preparing surfaces for additional layers, and optimizing the placement of vias or interconnections to improve the reliability and manufacturability of three-dimensional ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two or more fully processed wafers are bonded together for three-dimensional integration, then the functionality and performance of integrated circuits are improved, but alignment precision deteriorates due to wafer curvature and surface variations
Solution Approach 1:
The patent applies preliminary action by preparing the wafer backside surface in advance through specific processing steps (etching, cleaning, and applying adhesive layers) before bonding. This preliminary preparation ensures that the backside surface has the required flatness and surface quality, enabling precise alignment when multiple wafers are stacked together for three-dimensional integration.
2Adaptability or versatility
If chip size is increased to accommodate more transistors, then functionality is improved, but manufacturing cost increases due to fewer chips per wafer
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by bonding multiple wafers together. This dimensional change allows more functionality to be achieved within a smaller footprint area, effectively increasing the functional density without proportionally increasing the manufacturing cost per unit of functionality.
3Speed
If feature sizes are reduced to improve performance, then speed is improved, but interconnect delay worsens due to increased resistance and capacitance
Solution Approach 1:
The patent employs three-dimensional stacking to create vertical interconnect pathways that can provide alternative routing paths. This reduces the horizontal distance signals must travel across large chip areas, thereby reducing R-C delay and improving interconnect reliability while maintaining small feature sizes for high-performance transistors.
4Shape
If processed wafers are bonded in opposite directions with silicon substrate facing outwards, then structural symmetry is improved, but flatness control worsens due to varying curvature
Solution Approach 1:
The patent applies local quality by treating the backside surface of each wafer differently from the frontside. The backside undergoes specific processing (etching, cleaning, adhesive application) to achieve the required flatness and surface properties, while the frontside with the silicon substrate and circuitry maintains its original structure. This localized differentiation allows the bonded structure to achieve both symmetry and flatness.
Data Source
AI summary
Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks.