3D IC Terminal Layout for Reliable Die-to-Die Bonding
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Solution Overview
Problem
Existing three-dimensional integrated circuits face challenges with short circuits and disconnections of conductive terminals between vertically stacked dies, affecting power, performance, and area efficiency.
Innovation Solution
The solution involves arranging conductive terminals, such as edge bumps, at a distance greater than the minimum spacing from the functional block boundaries, ensuring they overlap or do not overlap the functional block, and using hybrid copper bonding to connect dies, thereby preventing bump sweep and improving signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conductive terminals are arranged close to the boundary of the functional block to maximize area utilization, then area efficiency is improved, but short circuits or disconnections may occur between vertically stacked dies
Solution Approach 1:
The patent applies local quality by differentiating the spacing requirements for different types of conductive terminals. Edge conductive terminals (which overlap the functional block) are spaced from the boundary by a first distance greater than or equal to a minimum distance, while non-edge conductive terminals (which do not overlap the functional block) are spaced by a second distance that can be smaller. This localized differentiation allows area optimization in non-critical regions while maintaining reliability in critical edge regions.
Solution Approach 2:
The patent segments the conductive terminals into two categories: edge conductive terminals that overlap the functional block and non-edge conductive terminals that do not overlap it. This segmentation allows different spacing strategies to be applied to each category, with edge terminals receiving more conservative spacing for reliability and non-edge terminals allowing tighter spacing for area efficiency.
2Power
If conductive terminals are arranged to overlap the functional block to improve electrical connection, then power and signal transmission are improved, but the risk of short circuits increases
Solution Approach 1:
The patent applies local quality by allowing only edge conductive terminals to overlap the functional block, while non-edge conductive terminals are positioned outside the functional block overlap region. This localized approach enables power and signal transmission through overlapping terminals where geometric alignment naturally provides better connection, while preventing short circuits by excluding non-edge terminals from the overlap region.
Solution Approach 2:
The functional block boundary acts as an intermediary that mediates between the need for overlapping connections and the need to prevent short circuits. By defining the boundary and establishing spacing rules relative to it, the patent creates a clear separation between regions where overlapping is permitted (edge regions with proper spacing) and regions where it is prohibited (non-edge regions).
Data Source
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Figure 2A
AI summary
Provided is a three-dimensional integrated circuit. The three-dimensional integrated circuit includes: a first die having a first surface and a second surface opposite each other; and a second die vertically stacked on the first surface of the first die. The first die includes: a functional block arranged on the first surface of the first die; and a plurality of conductive terminals arranged on the functional block and electrically connecting the first die to the second die. The plurality of conductive terminals include a plurality of edge conductive terminals arranged on an edge region of the functional block, and the plurality of edge conductive terminals are each spaced apart from a boundary of the functional block by a first distance that is greater than or equal to a minimum distance between the plurality of conductive terminals.