3D IC Through Via Formation via Segmented Etching
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Solution Overview
Problem
Three-dimensional integrated circuits (3DICs) face challenges in forming through vias with high depth-to-width aspect ratios, which complicates etching and can lead to issues with topography and flatness of bonding pads, affecting electrical connection and reliability.
Innovation Solution
A method involving the sequential formation of first and second openings in the dielectric layers and substrate, followed by bonding and forming a through via that directly contacts the bonding pad, using a diffusion barrier layer to prevent metal oxidation and improve electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through vias with high depth-to-width aspect ratios are formed in dielectric layers, then electrical connection between stacked dies is achieved, but etching complexity increases and topography/flatness control becomes difficult
Solution Approach 1:
The patent divides the single complex through-via etching process into multiple sequential steps: first forming a via through the first dielectric layer, then forming a second via through the substrate, and finally forming a third via through the second dielectric layer. Each step has a lower depth-to-width aspect ratio, reducing etching complexity while achieving the same electrical connection function.
Solution Approach 2:
The patent performs preliminary actions by forming opening structures and applying masking layers before final via formation. The masking layers are prepared in advance to define via patterns, and opening structures are created to guide subsequent etching steps, simplifying the overall process control.
2Reliability
If through vias with high depth-to-width aspect ratios are formed, then electrical connection is established, but topography and flatness of bonding pads deteriorate
Solution Approach 1:
The patent segments the via formation process into multiple shallower steps rather than one deep etching step. This segmentation maintains better topography control at each stage, as shallower etches cause less disturbance to the dielectric layer flatness and bonding pad topography.
3Ease of manufacture
If conventional via formation methods are used, then manufacturing process is simpler, but electrical connection reliability decreases
Solution Approach 1:
The patent applies preliminary actions by forming masking layers and opening structures before via etching. These preliminary structures guide the etching process precisely, ensuring reliable electrical connection while maintaining a manageable manufacturing process through systematic preparation steps.
Solution Approach 2:
The patent introduces masking layers as intermediary elements that facilitate precise via formation. These masking layers act as mediators between the design pattern and the physical via structure, enabling accurate positioning and shape control of vias for reliable electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity of etching through vias, enhances the topography and flatness requirements, and improves the electrical connection and reliability of 3DICs by forming a through via that directly contacts the bonding pad after bonding, thereby optimizing the electrical connection between chips.
Implementation Method 1
a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface
Data Source
AI summary
Three dimensional integrated circuit structures and manufacturing methods of the same are disclosed. The three dimensional integrated circuit structure includes a first chip and a second chip. The first chip is bonded to the second chip at a bonding interface. A through via of the first chip and a bonding pad of the second chip are electrically connected, and a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface.