3D IC Tier Bonding via Segmentation and Intermediary
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for manufacturing three-dimensional integrated circuits (3DICs) face challenges such as high costs, limited flexibility in active element creation, and potential damage from low-temperature processing, as well as space inefficiencies in interconnects like flip chip and through-silicon vias.
Innovation Solution
The method involves creating separate tiers of 3DICs with active elements on holding substrates, forming interconnection metal layers, and bonding them at relatively low temperatures, allowing for higher temperature processing and flexibility in active element creation, with the option to thin the second tier for increased via density and back gate biasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low temperature bonding process is used to transfer IC wafer, then wafer damage is reduced, but processing flexibility and active element creation capability are limited
Solution Approach 1:
The fabrication process is divided into separate stages: active elements are created on a first wafer at high temperatures, then the completed wafer is transferred to a second wafer at low temperatures for bonding. This segmentation allows each stage to operate under optimal conditions without compromising the other.
Solution Approach 2:
A second wafer acts as an intermediary substrate that receives the completed first wafer through low-temperature bonding. This intermediary allows the first wafer to be processed at high temperatures during active element creation without exposing it to thermal stress during subsequent bonding operations.
2Manufacturing precision
If higher temperature processing is used for active element creation, then active element performance is improved, but metal layer damage occurs
Solution Approach 1:
The process separates active element fabrication from interconnect formation into distinct stages performed on separate wafers. High-temperature processing is applied only during active element creation on the first wafer, while metal interconnect layers are formed later on the second wafer under lower temperature conditions.
Solution Approach 2:
The second wafer serves as a protective intermediary that receives the completed first wafer through low-temperature bonding. This allows high-temperature processing of active elements without exposing the metal interconnect layers to damaging temperatures, as the metal layers are formed after bonding on the second wafer.
3Adaptability or versatility
If flip chip or through-silicon via interconnects are used, then 3D integration is achieved, but space requirements increase
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical integration by stacking multiple wafers together. Wafer 1 is bonded to wafer 2, with active elements and interconnects distributed across different vertical layers, enabling three-dimensional circuit architecture that increases integration density.
Solution Approach 2:
The 3D integrated circuit is segmented into multiple separate wafers (wafer 1, wafer 2, etc.) that are fabricated independently and then bonded together. Each wafer contains specific active elements and interconnect layers, allowing modular design and reduced in-plane space requirements through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more flexible and efficient creation of 3DICs with reduced risk of metal damage, higher via density, and additional design flexibility, while minimizing space requirements.
Implementation Method 1
bonding them at relatively low temperatures
Data Source
AI summary
Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.