3D IC Through-Layer Vias for High-Density Interconnects
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Solution Overview
Problem
Current methods for constructing three-dimensional integrated circuits (3D ICs) face challenges such as limited TSV density due to misalignment issues, high temperature requirements for transistor processing, and performance limitations from vertical transistors, which hinder the development of high-density, low-power, and cost-effective 3D ICs.
Innovation Solution
The method involves layer transfer techniques using ion-cut operations to form monolithic layers of transistors with through-layer vias (TLVs) of diameters less than 150 nm, allowing for high-density interconnects and the use of horizontally oriented transistors in mono-crystalline silicon, enabling low-temperature processing and integration of different transistor types like replacement-gate, FinFet, and double gate transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Through Silicon Vias (TSVs) are used to connect bonded wafers in 3D ICs, then electrical connections between layers are achieved, but the density of TSVs is limited due to large diameter requirements (one to ten microns) and misalignment issues
Solution Approach 1:
The patent transitions from planar (2D) wafer bonding to three-dimensional (3D) stacking with vertically oriented transistors and interconnections. This dimensional change enables much higher interconnection density by utilizing the vertical dimension for both transistor orientation and interconnect routing, eliminating the need for large-diameter TSVs and achieving sub-100nm via dimensions.
Solution Approach 2:
The patent segments the monolithic structure into multiple layers with intermediate transfer layers. This segmentation allows for better alignment control between layers, as each layer can be independently processed and aligned to the layer below it, rather than requiring precise alignment across the entire wafer thickness.
2Ease of manufacture
If high temperature processing is used to create transistor elements, then useful transistor structures are formed, but the reliability of lower layer interconnect metallization and low-k intermetal dielectrics is compromised
Solution Approach 1:
The patent segments the fabrication process into temperature-staged steps: lower layers are formed with standard high-temperature processes, then transfer layers are added and processed at lower temperatures to form upper layer transistors. This segmentation allows each layer to be optimized for its specific temperature requirements, preserving the reliability of lower layer interconnects while enabling high-temperature transistor fabrication.
Solution Approach 2:
The patent performs preliminary formation of lower layer transistors and interconnects before adding upper layers. This preliminary action allows the lower layers to be fully processed and stabilized before subsequent layers are introduced, ensuring their reliability is not compromised by later high-temperature steps.
3Productivity
If device scaling is continued to enhance performance and reduce cost, then device speed increases and area decreases, but interconnection wiring dominates performance and power consumption
Solution Approach 1:
The patent moves from two-dimensional planar interconnects to three-dimensional vertical interconnects. This dimensional change dramatically shortens the average interconnect length by routing connections vertically through the stack rather than laterally across the chip, reducing both power consumption and performance limitations associated with long wiring paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the construction of high-density 3D ICs with improved performance, reduced power consumption, and lower costs by shortening wire lengths, increasing connectivity, and allowing for heterogeneous integration of components, thus extending Moore's Law and enabling more powerful and efficient devices.
Implementation Method 1
forming a layer transfer demarcation plane by an ion-cut operation
Data Source
AI summary
An Integrated Circuit device including: a first layer including first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer including second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors and a connection path between the second transistors and the second metal layer, where the connection path includes at least one through-layer via, and where the through-layer via has a diameter less than 150 nm.