3D IC Transistor Stacking with Single-Crystal Upper Layers
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Solution Overview
Problem
Current integrated circuit (IC) technologies are limited by two-dimensional (2D) integration methods, which restrict device density due to physical constraints and complex designs required for increased component integration, necessitating a three-dimensional (3D) IC structure with transistors at multiple levels to enhance density.
Innovation Solution
A 3D IC structure is formed by creating lower-level transistors on a semiconductor substrate and higher-level transistors using semiconductor pillars and fins, with epitaxial growth and laser annealing to achieve single-crystalline semiconductor layers for improved transistor performance, allowing for increased density without damaging lower-level circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional integration methods are used to increase device density, then more components can be integrated into a given area, but physical constraints and complex designs limit further density improvements
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking multiple transistor levels (first level, second level, third level) above the substrate. This dimensional change allows continued density improvement without proportionally increasing design complexity, as the vertical stacking provides a systematic approach to multi-level integration.
Solution Approach 2:
The patent implements nested structures where second-level transistors are formed above first-level transistors, and third-level transistors are formed above second-level transistors. Each level is nested within the vertical space occupied by the levels below, maximizing space utilization and achieving high density without excessive design complexity.
2Reliability
If laser annealing is used to create single-crystalline semiconductor layers, then transistor performance is improved, but there is risk of damaging lower-level circuitry
Solution Approach 1:
The patent applies laser annealing locally to specific regions where single-crystalline semiconductor layers are being formed at higher levels, rather than uniformly treating the entire structure. This localized approach improves transistor performance in the targeted areas while minimizing thermal exposure and potential damage to lower-level circuitry.
Solution Approach 2:
The patent employs intermediate layers and structural design that act as thermal barriers or cushioning between the laser annealing zone and lower-level circuitry. These protective structures absorb or redirect thermal energy, preventing damage to sensitive lower-level components during the high-temperature annealing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances device density by enabling the formation of single-crystalline semiconductor layers above lower-level transistors, facilitating the creation of higher-level transistors, thus overcoming the limitations of 2D integration and improving IC performance.
Implementation Method 1
The laser is removed from the reaction chamber, and the amorphous semiconductor layer is melted and crystallized to form single-crystalline semiconductor plugs 142 and single-crystalline semiconductor film 144.
Implementation Method 2
The amorphous semiconductor layer is melted and crystallized to form single-crystalline semiconductor plugs 142 and single-crystalline semiconductor film 144.
Implementation Method 3
forming a first epitaxial layer over the semiconductor substrate and the semiconductor pillars
Data Source
AI summary
An IC structure includes a first transistor, a dielectric layer, a plurality of semiconductor pillars, a plurality of semiconductor plugs, a semiconductor structure, and a second transistor. The first transistor is formed on a substrate. The dielectric layer is above the first transistor. The semiconductor pillars extend from the substrate into the dielectric layer. The semiconductor plugs extend from a top surface of the dielectric layer into the dielectric layer to the plurality of semiconductor pillars. The semiconductor structure is disposed over the top surface of the dielectric layer. The second transistor is formed on the semiconductor structure.