3D IC Mono-Crystallized Transistors Via Design
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Solution Overview
Problem
Current 3D stacked integrated circuits face challenges in constructing transistors above wiring layers at temperatures below 400°C, leading to degraded wire performance and limited connectivity between layers due to misalignment and high defect densities, which hinders the development of true 3D ICs with high-density connections.
Innovation Solution
The implementation of a 3D IC device with mono-crystallized transistors interconnected by metal layers, a global power grid, and local power grids, where the metal layers are between the semiconductor layers, and through-layer vias with radii less than 150 nm, along with thermally conductive paths to an external surface, allowing for high-density vertical connections and efficient heat removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are constructed in 3D stacked layers with high-temperature processing (above 700°C), then transistor performance and density improve, but the bottom wiring layer gets damaged due to exposure to high temperatures
Solution Approach 1:
The patent divides the 3D IC structure into separate temperature zones: the bottom layer uses temperature-resistant materials (tungsten, cobalt, platinum) capable of withstanding 700-900°C processing, while the top layer uses conventional copper wiring that requires lower temperatures. This segmentation allows each layer to be optimized for its specific temperature requirements, enabling high-density transistor stacking without damaging the interconnect structure.
Solution Approach 2:
The patent changes the material parameters of the interconnect layers to match different temperature regimes. By substituting copper with high-temperature-resistant materials (tungsten, cobalt, platinum) in the bottom layer and using them as barrier/seed layers for copper in the top layer, the system can tolerate the thermal stress of high-temperature transistor fabrication while maintaining low-resistance interconnects where needed.
2Manufacturing precision
If wafer bonding is performed with large contact landing pads to accommodate misalignment, then alignment tolerance improves, but connectivity density between layers decreases significantly
Solution Approach 1:
The patent performs preliminary alignment marker placement and wafer bonding preparation before actual bonding, using the temperature-resistant interconnect materials to create stable reference structures. The bottom layer interconnects are formed first with precise positioning, then the top layer is bonded onto them with alignment markers that guide the bonding process, enabling high-density connectivity while maintaining alignment tolerance.
Solution Approach 2:
The patent uses temperature-resistant materials (tungsten, cobalt, platinum) as intermediary barrier and seed layers between the silicon substrate and copper interconnects. These intermediary layers provide a stable, thermally-stable interface that facilitates precise alignment and bonding while protecting the underlying structure, enabling high-density vertical interconnects without requiring large landing pads.
3Productivity
If through-silicon via (TSV) contacts are made with small lateral dimensions to increase density, then connectivity density improves, but etching and filling becomes difficult
Solution Approach 1:
The patent introduces temperature-resistant materials (tungsten, cobalt, platinum) as intermediary barrier and seed layers that line the TSV holes before copper filling. These intermediary layers provide mechanical support and adhesion for the copper fill process in small-diameter vias, making it feasible to manufacture high-density TSVs with sub-100nm lateral dimensions while maintaining process reliability.
Solution Approach 2:
The patent creates a composite interconnect structure within TSVs, combining temperature-resistant materials (tungsten, cobalt, or platinum) as barrier/seed layers with copper as the primary conductive material. This composite approach enables the TSVs to maintain structural integrity and electrical performance at small dimensions, overcoming the manufacturing difficulties of pure-copper or single-material vias.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the construction of 3D ICs with high-density connections and improved heat removal, addressing the limitations of existing technologies by maintaining transistor performance and reducing thermal resistance, thus enhancing the reliability and yield of complex 3D systems.
Implementation Method 1
a first semiconductor layer comprising first mono-crystallized transistors, wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising aluminum or copper
Implementation Method 2
said global power grid is connected to said local power grid by a plurality of through second layer vias
Implementation Method 3
a plurality of thermally conductive paths from said second mono-crystallized transistors to an external surface of said device
Data Source
AI summary
A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.