3D Integrated Circuit Diffusion Trapping Region for Metal Ion Blocking
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Solution Overview
Problem
Metal ions such as Cu, Fe, or Na from structures like through-Si-vias and metal electrodes in integrated circuits can diffuse into transistor structures, causing performance degradation or failure, and existing ion implantation methods often damage dielectric layers and through-Si-vias.
Innovation Solution
A 3D integrated circuit structure with a diffusion trapping region formed on the semiconductor substrate surrounding through-Si-vias, using ions like Ar, Xe, Ge, or P to trap metal ions, with controlled implantation depth and dose, and a method involving self-alignment and protection layers to prevent ion diffusion into sensitive areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is used to trap metal ions, then metal ion diffusion is prevented, but dielectric layers and through-Si-vias are damaged
Solution Approach 1:
The patent applies local quality by creating a diffusion trapping layer with specific spatial localization around through-Si-vias. The layer is formed only in regions where metal ion diffusion is problematic, using selective ion implantation targeted at areas surrounding the via structures. This localized approach prevents metal ion diffusion into transistor structures while avoiding damage to dielectric layers and through-Si-vias that would result from blanket ion implantation across the entire substrate.
2Reliability
If ion implantation is performed to trap metal ions, then diffusion is blocked, but structures outside target regions are damaged
Solution Approach 1:
The patent employs preliminary action by forming the diffusion trapping layer through selective ion implantation before subsequent processing steps. The trapping layer is created in advance with precise spatial control, positioning it exactly where metal ion diffusion needs to be blocked. This preliminary, precisely-targeted implantation prevents the need for later corrective actions and avoids damage to non-target regions that would occur with less precise implantation methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The diffusion trapping region effectively blocks metal ions from entering semiconductor devices and dielectric layers, enhancing the reliability of the integrated circuit by preventing performance degradation and failure, while minimizing damage to the through-Si-vias.
Implementation Method 1
The implanted ions comprise any one or more of Ar, Xe, Ge, or P. The implantation depth is controlled to be 10-1000 nm. The implantation dose is 10^13-10^16/cm^2.
Implementation Method 2
Metal ions such as Cu, Fe, or Na ions from structures such as through-Si-via (TSV), interconnection structure, or metal electrode of semiconductor device, to diffuse into transistor structures and interconnection structures
Data Source
AI summary
The present invention provides a 3D integrated circuit and a manufacturing method thereof. The circuit structure comprises: a semiconductor substrate; at least one semiconductor device formed on the upper surface of the semiconductor substrate; a through-Si-via through the semiconductor substrate and comprising an insulating layer covering sidewalls of the through-Si-via and conductive material filled in the insulating layer; an interconnection structure connecting the at least one semiconductor device and the through-Si-via; and a diffusion trapping region formed on the lower surface of the semiconductor substrate. The present invention is applicable in manufacture of the 3D integrated circuit.