3D IC Upper-Stage Protection Using TSV Charge Drainage
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Solution Overview
Problem
Existing solutions for mitigating antenna effects in 3D integrated circuits are either ineffective in draining electric charges or require significant resources, making them unsuitable for VLSI applications.
Innovation Solution
A process involving two semiconductor substrates, where the second substrate includes through-substrate via and protective components to drain electric charges, is used to effectively connect and protect electronic components against antenna effects during plasma etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy transistors are used to drain electric charges, then protection against antenna effects is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary substrate (second substrate) with through-substrate vias that acts as a mediator to drain electric charges away from the oxide layer. This intermediary structure provides a dedicated charge drainage path without requiring complex modifications to the electronic components themselves, thus improving protection while maintaining reasonable device complexity.
Solution Approach 2:
The patent segments the charge drainage function from the electronic components by creating a separate substrate structure with through-substrate vias. This segmentation allows the charge drainage function to be implemented independently, avoiding the need to modify each electronic component with dummy transistors, thereby reducing overall device complexity.
2Reliability
If p-n junctions are used to drain electric charges, then protection against antenna effects is improved, but device complexity increases
Solution Approach 1:
The patent uses an intermediary substrate with through-substrate vias as a mediator to drain electric charges. This approach avoids the complexity of forming and configuring p-n junctions within each electronic component, while still providing effective charge drainage protection against antenna effects.
Solution Approach 2:
The charge drainage function is segmented into a separate substrate layer with through-substrate vias, independent of the electronic components. This segmentation eliminates the need for complex p-n junction formation within each component, reducing device complexity while maintaining protection effectiveness.
3Reliability
If metal hops are used during sequential fabrication, then accumulation of electric charges is decreased, but interconnect line resources are significantly consumed
Solution Approach 1:
The patent introduces an intermediary substrate with through-substrate vias that provides a dedicated charge drainage path. This mediator structure eliminates the need for extensive metal hops and additional interconnect lines, as the charge drainage function is handled by the substrate structure itself, thereby reducing interconnect line resource consumption.
Solution Approach 2:
The charge drainage function is segmented into the substrate structure with through-substrate vias, separate from the interconnect lines. This segmentation allows charge drainage to be achieved without consuming valuable interconnect line resources that would otherwise be required for metal hops.
4Ease of manufacture
If existing prior-art solutions are used in 3D integration, then fabrication process is simpler, but electric charges are not effectively drained
Solution Approach 1:
The patent transitions from planar charge drainage approaches to a three-dimensional approach by implementing through-substrate vias that extend vertically through the substrate. This dimensional change enables effective charge drainage in 3D integrated circuits, addressing the limitation of prior-art solutions while maintaining compatibility with 3D integration fabrication processes.
Solution Approach 2:
The patent changes the electrical parameters of the substrate by introducing through-substrate vias with specific conductivity characteristics. This parameter change enables the substrate to effectively drain electric charges, transforming it from a passive support structure to an active charge drainage pathway, thereby improving reliability without complicating the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process effectively drains electric charges from the metal surface of the metallization levels, preventing damage to the oxide layer and enhancing the protection of electronic components against antenna effects in 3D integration.
Implementation Method 1
the through-substrate via is electrically connected to the last metallization level of the first stack
Implementation Method 2
The etch in the plasma P requires a biasing electrode E1
Data Source
AI summary
A process for protecting an upper stage of an electronic components against antenna effects includes providing a first structure having a first substrate with a first surface, a first stage of electronic components formed in a second surface of the first substrate, and a first stack having a last metallization level electrically connected to the second surface; and providing a second structure having a second substrate with a through-substrate via and having a second stage of electronic components having protective components that are arranged to drain electric charges to the second substrate. The process also includes joining the first and second structures so that the through-substrate via is electrically connected to the last metallization level of the first stack and forming a second stack on the second stage having a first metallization level electrically connected to the through-substrate via and to the first surface of the second substrate.