3D IC TSV Cell Layout for Antenna and ESD Protection

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Solution Overview

Problem

The antenna effect, which occurs during the manufacturing of integrated circuits due to electrostatic charge accumulation, poses yield and reliability issues, particularly in 3D ICs with TSV and HB structures, as it can degrade gate oxide strength and cause MOS device failures, and existing solutions often require additional chip area or increase power consumption.

Innovation Solution

Placing an antenna diode in the TSV cell or HB region, rather than within specific functional cells, provides centralized protection for neighboring transistors, utilizing otherwise unused chip area and reducing power consumption, while also enlarging the poly area of transistors for enhanced protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If antenna diodes are placed within specific functional cells to protect transistors, then transistor protection against antenna effect is improved, but chip area utilization deteriorates and power consumption increases

Engineering Contradiction:

Improvetransistor protectionVSAvoidchip area utilization

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the antenna effect protection function with the TSV cell structure by placing antenna diodes within the TSV cell region. This consolidates protection for multiple neighboring transistors into a single location, improving chip area utilization while maintaining reliability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The TSV cell region is given multiple functions: it serves both as the through-silicon via structure for 3D IC interconnection and as a centralized protection zone for antenna effect mitigation. This multi-functional approach eliminates dedicated protection area while maintaining transistor safety.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If antenna diodes are placed within specific functional cells to protect transistors, then transistor protection against antenna effect is improved, but power consumption increases

Engineering Contradiction:

Improvetransistor protectionVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If poly area of transistors is enlarged for antenna effect protection, then protection effectiveness is improved, but device density deteriorates

Engineering Contradiction:

Improveantenna effect protectionVSAvoiddevice density

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the protection function from the transistor structure itself, placing antenna diodes in the TSV cell region rather than enlarging transistor poly areas. This separates protection functionality into a dedicated zone, maintaining high device density while providing effective antenna effect mitigation.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively mitigates the antenna effect, improving chip area utilization, IC speed, and power efficiency by centralizing the antenna diode's protective function within the TSV or HB regions, thus enhancing the reliability and performance of 3D ICs.

Implementation Method 1

The antenna effect, which occurs during the manufacturing of integrated circuits due to electrostatic charge accumulation

Methodology Applied

Scientific EffectElectrostatic discharge: Electrostatic Discharge

Data Source

PatentUS11824254B2Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit

Publication Date: 2023.11.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.