3D IC Package Underfill and Molding for Warping Control
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing circuit density due to physical constraints in two-dimensional (2D) ICs, prompting the need for three-dimensional (3D) ICs, which require innovative manufacturing processes to overcome challenges like overhang structures and warping during package handling.
Innovation Solution
A chip package structure and method using a CoWoS-like process flow that skips substrate bonding, where a larger second die is positioned on a first die encapsulated in a molding compound, with an underfill injected between them, and both encapsulated in a second molding compound, providing mechanical support and electrical coupling through a redistribution layer and ball grid array (BGA) connectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substrate bonding is used in CoWoS process flow, then electrical connections between dies are achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the substrate bonding step from the traditional CoWoS process flow. By directly attaching the interposer wafer to the packaging substrate without intermediate bonding steps, the manufacturing process is simplified while maintaining electrical connectivity through the interposer's TSV structures and conductive layers.
Solution Approach 2:
The patent segments the packaging process into distinct modular steps: interposer wafer preparation with TSVs and conductive layers, die attachment to interposer, and final packaging substrate attachment. This segmentation allows each step to be optimized independently and simplifies the overall manufacturing flow by removing the substrate bonding step.
2Quantity of substance
If more devices are integrated into one chip, then circuit density increases, but design complexity and warping issues increase
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical integration by stacking multiple dies on the interposer wafer. This dimensional change allows significantly higher circuit density without increasing the footprint area, while the interposer provides mechanical support that prevents warping issues associated with high-density integration.
Solution Approach 2:
The interposer wafer acts as an intermediary between multiple dies and the packaging substrate. It provides mechanical support to prevent warping, enables electrical interconnection through TSVs and conductive layers, and simplifies the attachment process by serving as a stable platform for die stacking.
3Quantity of substance
If die size is reduced, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
By moving to 3D stacking architecture, the patent achieves higher integration density without further reducing the lateral dimensions of individual dies. This allows manufacturing processes to operate at existing precision levels while still increasing overall device capacity through vertical stacking.
Data Source
AI summary
A chip package may include: a first die; a second die; an underfill disposed between and in physical contact with the first die and the second die; and one or more conductive elements encapsulated in the underfill and coupling the first die and the second die to each other.