3D-IC Mixed Placement via 2D Unfolding for Cross-Die Timing
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Solution Overview
Problem
Current methods for implementing three-dimensional integrated circuit (3D-IC) designs, particularly Memory-on-Logic 3D-IC, face challenges in optimizing performance, power, and area due to the limitations of die-by-die implementation, which requires manual co-design and struggles with accurate timing budgeting and modeling across dies.
Innovation Solution
An approach that involves mixed placement of macros and standard cells using two-dimensional unfolding and shadow bump assignment, allowing concurrent optimization of timing, density, wire length, and floorplan constraints, eliminating the need for die-by-die iteration and enabling simultaneous optimization across multiple dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If die-by-die implementation method is used for 3D-IC design, then each die can be implemented separately with existing EDA tools, but timing budgeting accuracy deteriorates and manual co-design iteration is required
Solution Approach 1:
The patent merges multiple dies into a single unified design space by unfolding the 3D stacked architecture into a 2D representation. This allows the EDA tool to perform placement and routing across all dies simultaneously without requiring separate die-by-die implementation, thereby eliminating timing budgeting errors while maintaining manufacturability through the unfolding transformation.
Solution Approach 2:
The patent transforms the three-dimensional stacked die architecture into a two-dimensional unfolded layout for design optimization purposes. This dimensionality change enables concurrent optimization across all dies in a single EDA tool instance, improving timing accuracy while the final implementation remains in 3D stacked form.
2Ease of operation
If manual co-design method is used for Memory-on-Logic 3D-IC, then placement can be performed separately on each die, but optimization of cross-die timing paths deteriorates
Solution Approach 1:
The patent combines the placement processes of multiple dies into a single concurrent optimization step by unfolding the 3D architecture. This allows the EDA tool to simultaneously optimize macro and standard cell placements across all dies, ensuring optimal cross-die timing paths without requiring manual co-design iteration.
Solution Approach 2:
The patent introduces an intermediary unfolding transformation that converts the 3D stacked die structure into a 2D layout where cross-die connections become visible and optimizable within a single EDA tool instance. This intermediary representation enables automatic optimization of timing paths that span multiple dies.
3Ease of manufacture
If die-by-die flow is used with bump assignment, then connecting structures can be placed, but design iteration is required to optimize PPA results
Solution Approach 1:
The patent performs preliminary bump assignment and connection structure placement in the unfolded 2D representation before finalizing the 3D implementation. This preliminary action allows all bump locations and inter-die connections to be optimized simultaneously in a single pass, eliminating the need for iterative redesign between dies.
Solution Approach 2:
The patent merges bump assignment and connection optimization across all dies into a single concurrent process by working in the unfolded 2D space. This eliminates the sequential die-by-die iteration process, significantly improving design productivity while maintaining manufacturability.
Data Source
AI summary
Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.