3D IC Testing via Universal Circuit and Series Connection
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Solution Overview
Problem
Current three-dimensional integrated circuit testing technologies face inefficiencies in testing terminal connections both before and after layering multiple chips, with existing methods requiring different test circuits and struggling to reduce overall test area and time as the number of layered chips increases.
Innovation Solution
A three-dimensional integrated circuit design that incorporates a pair of connections, including a test signal generation circuit and a test result judgment circuit, on each chip, allowing for efficient testing of conducting states before and after layering by forming series connections and using the same test circuits for both pre- and post-layering tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different test circuits are used for pre-layering and post-layering tests, then testing coverage is improved, but device complexity and test area increase
Solution Approach 1:
The patent implements a universal test circuit design where the same test circuit on each chip can perform both pre-layering tests (testing individual chip terminals) and post-layering tests (testing inter-chip connections through TSVs). The test circuit includes a test signal generation unit and a test result judgment unit that can operate in different modes depending on whether chips are layered or not, eliminating the need for separate test circuits for different testing stages.
2Measurement precision
If multiple dedicated terminals are provided for testing, then testing accuracy is improved, but area of stationary object increases
Solution Approach 1:
The patent uses a universal test circuit that can test multiple terminals (both first and second terminals) without requiring separate dedicated test circuits for each terminal. The test signal generation circuit can sequentially or simultaneously drive different terminals, and the test result judgment circuit can evaluate responses from different terminals, achieving comprehensive testing coverage with a single compact test circuit block on each chip.
3Manufacturing precision
If series connection testing is performed before layering, then manufacturing precision is improved, but loss of time occurs due to additional test steps
Solution Approach 1:
The patent performs preliminary testing of terminal connections (first terminal and second terminal) in series connection before the chips are layered. The test signal generation circuit generates a test signal that travels through the series connection of terminals, and the test result judgment circuit evaluates the conducting state. This preliminary test ensures connection accuracy before layering, and because the same universal test circuit is used, no additional test equipment or time is required after layering - the same circuit can re-test the connections through the TSVs.
Data Source
AI summary
Each chip in a three-dimensional circuit includes a pair of connections, a test signal generation circuit, and a test result judgment circuit. The connections are electrically connected with an adjacent chip. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives a signal from the other of the connections and, from the state of the signal, detects the conducting state of the transmission path for the signal. Before layering the chips, a conductor connects the connections to form a series connection, and the conducting state of each connection is detected from the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between the chips is tested.