3D IC Circuit Units With Vertical Buses for Wire Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The performance and functionality of Integrated Circuits (ICs) are hindered by degrading wire performance due to 'scaling', which is not effectively addressed by existing 3D stacking technologies, leading to increased power consumption and limited integration capabilities.
Innovation Solution
The development of multilayer Three Dimensional Integrated Circuit (3D IC) devices utilizing layer transfer techniques, including hybrid bonding and epitaxial layer transfer, to create a 3D structure with multiple electronic circuit units, vertical data buses, and control lines, enabling efficient electrical connections and heterogeneous integration of various components like MEMS sensors and memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling is applied to reduce component sizes, then transistor performance and density improve, but wire performance degrades
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical stacking, organizing transistors and wires into multiple stacked layers. This dimensional change allows transistors to be positioned vertically above each other, dramatically reducing horizontal wire lengths while maintaining high transistor density. The 3D architecture separates transistor placement from wire routing, enabling independent optimization of both.
2Speed
If 3D stacking is implemented to reduce wire lengths, then wiring delay decreases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated circuit into multiple discrete stacked layers, each containing specific transistor types and wire routing patterns. This segmentation allows independent design, fabrication, and testing of individual layers before assembly. Each layer can be optimized for specific functions (e.g., logic, memory, I/O) while maintaining standardized interfaces for stacking.
Solution Approach 2:
The patent prepares stacking interfaces and connection structures in advance during the fabrication of individual layers. Alignment marks, bonding pads, and through-silicon via structures are formed preliminarily on each layer before stacking, ensuring precise registration and reducing assembly complexity. This preliminary preparation enables automated stacking processes.
3Adaptability or versatility
If traditional 3D stacking methods are used, then integration capability improves, but power consumption increases
Solution Approach 1:
The patent implements heterogeneous stacking where different layers contain different transistor technologies optimized for specific functions. High-performance transistors are placed in logic layers requiring speed, while low-power transistors are used in memory layers. Power consumption is optimized locally in each layer based on functional requirements, and short vertical connections reduce overall power loss.
Data Source
AI summary
A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; and at least eight electronic circuit units (ECUs), where each of the at least eight ECUs includes a first circuit, the first circuit including a portion of the first transistors, where each of the at least eight ECUs includes a second circuit including a portion of the second transistors, where each of the at least eight ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least eight ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.