3D IC Electronic Circuit Units With Vertical Bonded Interconnects
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Solution Overview
Problem
The performance and functionality of Integrated Circuits (ICs) are hindered by degrading wire performance due to scaling, which affects power consumption and efficiency, and existing 3D stacking techniques face challenges in layer transfer and integration, particularly in maintaining cost-effectiveness and yield.
Innovation Solution
The development of multilayer Three Dimensional Integrated Circuit (3D IC) devices utilizing layer transfer technologies that allow for the reuse of donor wafers and the integration of active devices, including hybrid bonding and Smart Alignment techniques, to create a 3D structure with multiple electronic circuit units and vertical connectivity structures, enabling efficient electrical connections and reduced development costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If 3D stacking is implemented to reduce wire lengths, then wiring delay is reduced, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional wire routing to three-dimensional vertical interconnects using TSVs. This dimensional change allows signals to travel shorter distances by moving vertically between stacked dies, directly reducing wiring delay while managing the added complexity through standardized vertical connection structures.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate semiconductor dies that are stacked and connected via TSVs. Each die can be independently designed, fabricated, and optimized, then assembled into a functional 3D system. This segmentation reduces the overall wire length within each individual die while the vertical connections provide efficient inter-die communication.
2Adaptability or versatility
If multiple layers of dies are constructed separately and bonded with TSVs, then 3D integration is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent performs all necessary circuit design, transistor fabrication, and wire routing on individual semiconductor dies before the stacking and bonding process. This preliminary completion of individual die manufacturing simplifies the overall process by allowing parallel fabrication of multiple dies that can then be assembled through standardized TSV bonding operations.
Solution Approach 2:
The patent uses TSVs as intermediary connection structures between stacked semiconductor dies. These TSVs serve as standardized interfaces that simplify the bonding process between layers, providing mechanical support and electrical connection in a uniform manner that reduces manufacturing complexity compared to custom interconnect solutions.
3Adaptability or versatility
If wire lengths are reduced through 3D stacking, then functionality is improved, but power consumption increases due to wire dominance
Solution Approach 1:
By implementing vertical interconnects through 3D stacking, the patent dramatically reduces the lateral wire lengths that dominate power consumption in traditional 2D ICs. The vertical TSV connections provide short, efficient pathways for signal and power transmission between stacked dies, reducing the total wire length and associated resistive power losses while enabling enhanced functionality.
Data Source
AI summary
A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; at least four electronic circuit units (ECUs); a redundancy circuit, where each of the at least four ECUs includes a first circuit, which includes a portion of the first transistors, where each of the at least four ECUs includes a second circuit, the second circuit including some second transistors, where each of the at least four ECUs includes a vertical connectivity structure which includes pillars, where the pillars provide electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one memory control circuit and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide and metal to metal bonding regions.