3D Gate-All-Around IC Layout for Dense Via Isolation
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Solution Overview
Problem
As integrated circuit devices are downscaled and become more integrated with multilayer structures, there is a need for reduced sizes and improved operational accuracy and speed, which existing technologies struggle to achieve effectively.
Innovation Solution
The integrated circuit device design includes a multilayer structure with gate contact vias and source/drain contact vias arranged in a line, and a decreasing separation distance between gate contact vias, utilizing a specific arrangement of insulating lines, channel lines, gate lines, and source/drain regions to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If integrated circuit devices are downscaled to reduce size, then device size decreases, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent transitions from planar 2D transistor arrangements to a 3D vertical stacking architecture. Multiple transistor layers are stacked vertically with gate lines extending in both horizontal and vertical directions, allowing continued size reduction while maintaining manufacturability through established lithographic processes adapted for three-dimensional structures.
Solution Approach 2:
The patent implements nested structures where gate lines are positioned both above and below channel lines, with insulating lines and contact structures integrated within the stacked layers. This nesting allows multiple functional elements to occupy overlapping spatial regions, reducing the overall device footprint while maintaining proper electrical isolation and connection.
2Area of stationary object
If gate contact vias and source/drain contact vias are arranged in a line with decreasing separation distance, then device area decreases, but risk of short circuits increases
Solution Approach 1:
The patent introduces insulating lines positioned between adjacent gate contact vias and source/drain contact vias. These insulating lines act as intermediary barriers that electrically isolate neighboring contacts, allowing them to be placed closer together without risking short circuits. The insulating material fills the space between conductive elements and prevents direct electrical connection.
Solution Approach 2:
The patent utilizes vertical stacking to separate contact structures into different layers. Gate contact vias and source/drain contact vias are positioned at different vertical levels, with insulating lines and barrier structures between layers preventing lateral short circuits while allowing reduced planar separation distance between contacts.
3Adaptability or versatility
If multilayer structures are used to increase integration density, then device functionality increases, but structural complexity increases
Solution Approach 1:
The patent designs gate lines and insulating lines that serve multiple functions simultaneously. Gate lines provide electrical control for transistors while also serving as structural support for vertical stacking. Insulating lines provide electrical isolation while defining structural boundaries for subsequent layers. This multi-functionality reduces the need for separate dedicated structures.
Solution Approach 2:
The patent divides the integrated circuit into discrete repeating units, each containing channel lines, gate lines, and insulating lines arranged in standardized layers. This segmentation allows complex multilayer structures to be built from modular building blocks, simplifying fabrication processes and reducing overall structural complexity through repetition of proven design units.
Data Source
AI summary
An integrated circuit device includes a lower insulating line extending in a first direction, a plurality of lower channel lines over the lower insulating line, first and second lower gate lines respectively on opposing sides of the lower insulating line and opposing sides of one of the lower channel lines, a third lower gate line extending around upper and lower surfaces of the one of the lower channel line and connecting the first and second lower gate lines to each other, an outer gate line arranged under the lower insulating line and contacting the first and second lower gate lines, an upper insulating line over an upper surface of each lower channel line, a plurality of upper channel lines over the upper insulating line, and an upper gate line extending around one of the upper channel lines.