3D IC Through-Via Protection Circuits for Plasma Damage
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Solution Overview
Problem
The plasma etching process during integrated circuit manufacturing can cause plasma-induced gate oxide damage, leading to yield and reliability issues due to charge accumulation in the gate poly, which is not addressed by existing technologies.
Innovation Solution
Incorporating protection circuits within a keep-out zone around through vias in a 3D integrated circuit to mitigate mechanical stress, thermal gradients, and electrical interference, using diodes to provide a current path for discharging excessive voltages and preventing damage to the gate dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If protection circuits are disposed outside the keep-out zone, then the circuits are easier to manufacture and less susceptible to mechanical stress, but the spatial overhead increases and manufacturing precision requirements are not met
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple integrated circuits in a 3D configuration, allowing protection circuits to be disposed in the keep-out zone of upper layers without interfering with active devices in lower layers. This dimensional transition enables space-efficient placement while maintaining protection functionality.
2Area of stationary object
If protection circuits are disposed in the keep-out zone, then spatial overhead is reduced, but the circuits are exposed to increased mechanical stress and manufacturing defects
Solution Approach 1:
The patent introduces an intermediary protective structure (the keep-out zone itself acting as a protective barrier) that isolates the protection circuits from the most severe mechanical stress and manufacturing defects. The keep-out zone serves as a buffer region that absorbs harmful effects while allowing the protection circuits to function effectively.
3Productivity
If through vias are manufactured with smaller dimensions, then integration density increases, but plasma-induced gate oxide damage becomes more severe
Solution Approach 1:
The patent extracts the protection function from the active circuit areas and places dedicated protection circuits in the keep-out zone. These protection circuits specifically address plasma-induced gate oxide damage by providing charge dissipation paths, thereby protecting the gate dielectric integrity while allowing high-density through via manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces spatial overhead and enhances the reliability and performance of the integrated circuit by minimizing adverse effects from manufacturing defects and electrical interference, while efficiently utilizing the circuit area.
Implementation Method 1
using diodes to provide a current path for discharging excessive voltages and preventing damage to the gate dielectric
Implementation Method 2
provide a current path for discharging excessive voltages
Data Source
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AI summary
A 3D integrated circuit includes a first integrated circuit including a first substrate. A second integrated circuit is stacked on the first integrated circuit. A through via extends through the first substrate and electrically connects the first integrated circuit and the second integrated circuit to one another. A plurality of protection circuits is disposed at opposite sides of the through via in a keep-out zone surrounding the through via and is electrically connected to the through via.