3D IC Voltage Stacking for Lower IR Drop and Fewer Power Bumps
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Solution Overview
Problem
The challenge in 3D integrated circuits (3D ICs) is the increasing power density with the number of stacked dies, leading to higher IR drop and the need for more power bump resources, which is costly and challenging to scale down.
Innovation Solution
A 3D IC design with a package wiring plane, die stack, metal interconnect layer, and pass-through interconnects that divide the voltage difference across stacked dies, reducing current density and package bumps, using identical dies for uniform power distribution and bypassing internal connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked dies is increased to achieve higher circuit density, then the circuit density is improved, but the power density increases leading to higher IR drop and requiring more power bump resources
Solution Approach 1:
The power delivery network is segmented into multiple voltage domains, with each stacked die operating in its own voltage domain. This segmentation allows the total package voltage to be distributed across multiple dies in series, reducing the current required for power delivery while maintaining high circuit density through vertical stacking
Solution Approach 2:
The patent transitions from a conventional 2D power distribution approach to a 3D voltage stacking approach. By utilizing the vertical dimension and stacking dies with series-connected voltage domains, the system achieves higher circuit density without proportionally increasing power density, as the voltage is distributed across the vertical stack rather than being concentrated in a single plane
2Reliability
If more power bump resources are allocated to handle increased power density, then the IR drop is reduced, but the package footprint and cost increase
Solution Approach 1:
The patent changes the voltage parameter distribution across the die stack by implementing series-connected voltage domains. Instead of maintaining uniform voltage across all dies, the system distributes the total voltage across multiple dies in series, which reduces the current required and thereby reduces IR drop without increasing the number or size of power bumps, keeping the package footprint compact
3Length of moving object
If feature size is reduced to scale down devices, then the device dimensions are decreased, but the manufacturing complexity and cost increase
Solution Approach 1:
Instead of continuing to scale down feature sizes in the lateral dimension, the patent utilizes the vertical dimension by stacking multiple dies. This approach maintains larger, more manufacturable feature sizes while achieving higher device density through vertical integration, thereby reducing manufacturing complexity and cost associated with extreme feature size reduction
Data Source
AI summary
In an aspect there is provided a 3D IC device comprising: a package wiring plane comprising a global VDD voltage node and a global VSS voltage node; a die stack arranged over the package wiring plane and comprising a number of stacked dies stacked on top of each other; a metal interconnect layer arranged on top of a top stacked die of the die stack; and a pass-through interconnect extending vertically through each stacked die of the die stack and connecting the metal interconnect layer to the global VDD voltage node; wherein each stacked die of the die stack has a bottom side and a top side, a local VDD voltage contact on its top side and a local VSS voltage contact on its bottom side.