3D Image Sensor Fabrication via Front-Side Transistor Stacking
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Solution Overview
Problem
Existing image sensor technologies, such as CMOS and CCD sensors, face interference from metal interconnects and gate oxides deposited on the top side of the substrate, which degrade picture quality and reduce photodiode sensitivity due to blocked light paths, limiting quantum efficiency and full well capacity.
Innovation Solution
The method involves fabricating control transistors on the front side of the image sensor, opposite the image collecting surface, allowing for increased full well capacity and fill factor by reducing interference from top-side structures and enabling more light to reach the photosensitive region, while allowing for separate optimization of frontside circuitry fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal interconnects and gate oxides are deposited on the top side of the substrate, then device functionality is achieved, but light path is blocked and photodiode sensitivity is reduced
Solution Approach 1:
The patent inverts the conventional architecture by placing metal interconnects and gate oxides on the front side (light-entry side) of the substrate instead of the back side. This allows light to enter the substrate and reach the photosensitive region without being blocked by metal structures, while the circuitry remains functional on the opposite side.
Solution Approach 2:
The patent transitions from a planar 2D layout where circuitry and photosensitive regions share the same surface to a 3D stacked architecture. Control transistors are positioned in a different spatial dimension (on the front side) relative to the photosensitive region (on the back side), allowing both functions to coexist without interference.
2Reliability
If substrate thickness is reduced to allow light entry, then quantum efficiency is improved, but structural strength is reduced
Solution Approach 1:
Instead of thinning the substrate to allow light entry, the patent inverts the approach by placing the photosensitive region on the back side and allowing light to enter through the front side. This maintains full substrate thickness for structural strength while achieving the same light-entry objective.
3Reliability
If photodiode area is increased to improve light collection, then fill factor is improved, but die size must be expanded
Solution Approach 1:
The patent utilizes the third dimension by stacking the control transistor layer above the photosensitive region layer. This vertical integration allows the photodiode area to be maximized for high fill factor without requiring proportional expansion of the overall die footprint, as the circuitry occupies the vertical space rather than lateral space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the sensitivity and efficiency of image sensors by increasing the fill factor and light collection area without expanding the die size, resulting in improved image gathering capabilities and reduced noise in the photodiode array.
Implementation Method 1
a photodiode having a photosensitive region that converts received electromagnetic energy, such as light, into electrical charge
Data Source
AI summary
A system and method for fabricating a 3D image sensor structure is disclosed. The method comprises providing an image sensor with a backside illuminated photosensitive region on a substrate, applying a first dielectric layer to the first side of the substrate opposite the substrate side where image data is gathered, and applying a semiconductor layer that is optionally polysilicon, to the first dielectric layer. A least one control transistor may be created on the first dielectric layer, within the semiconductor layer and may optionally be a row select, reset or source follower transistor. An intermetal dielectric may be applied over the first dielectric layer; and may have at least one metal interconnect disposed therein. A second interlevel dielectric layer may be disposed on the control transistors. The dielectric layers and semiconductor layer may be applied by bonding a wafer to the substrate or via deposition.