3D In-Memory Computing Device with Stacked BEOL Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current in-memory computing (IMC) architectures face limitations in performance and power efficiency due to frequent data movement between memory and processing units, which is inherent in the von Neumann architecture, particularly in performing complex matrix operations required for deep neural networks like CNNs.
Innovation Solution
A 3D IMC device is designed with a memory layer of FEOL memory cells and a logic layer of vertically stacked BEOL transistors, where each transistor operates as a multiplier, sharing input data lines and performing multiplication and accumulation operations directly within the memory array, enhancing spatial efficiency and reducing latency through vertical data movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is moved frequently between memory and processing units in von Neumann architecture, then processing can be performed, but performance and power efficiency deteriorate due to data movement overhead
Solution Approach 1:
The patent merges memory and processing functions into a single integrated structure where FEOL memory cells store data and BEOL transistors perform computing operations in the same physical location, eliminating data movement between separate memory and processing units
Solution Approach 2:
The patent transitions from a 2D planar architecture to a 3D vertical architecture by stacking BEOL transistors vertically on top of FEOL memory cells, enabling in-memory computing without increasing planar footprint and reducing data movement distance
2Productivity
If more transistors are added to perform matrix operations, then computing capability improves, but device area increases
Solution Approach 1:
The patent uses vertical stacking of BEOL transistors on top of FEOL memory cells to add computing capability in the vertical dimension rather than expanding horizontally, maintaining compact planar footprint while increasing operational capacity
Solution Approach 2:
The integrated memory-transistor structure serves dual functions: FEOL memory cells store data while BEOL transistors perform computing operations, allowing the same physical space to fulfill both storage and processing roles simultaneously
Data Source
AI summary
An apparatus including a memory layer including a plurality of front-end-of-line (FEOL) memory cells and a logic layer including plural arithmetic logic gates including back-end-of-line (BEOL) transistors, the plurality of BEOL transistors being vertically stacked on respective upper ends of the plurality of memory cells, wherein each of multiple transistors of the plurality of BEOL transistors operates as a multiplier and is configured to provide an operation result with respect to first values stored in corresponding memory cells of the plurality of memory cells.