3D Inductor-Capacitor Array Layout for Higher Power Modules
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Solution Overview
Problem
The existing integration methods for power supply modules, particularly in multi-phase power supply systems, face limitations in inductor size due to module size constraints, leading to reduced power output and increased complexity in wiring, resulting in low utilization and high costs of inductor and capacitor materials.
Innovation Solution
A device module and manufacturing method that includes a lamination structure with inductors and capacitors arranged in layers, where inductors are formed along the thickness direction with via electrodes for electrical coupling, and a driver chip is integrated to simplify the layout and wiring, increasing the footprint of inductors and improving power output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the conventional integration method arranges inductor, capacitor and integrated circuit into a package to form power supply module, then the module can be assembled, but the inductor size is greatly limited due to module size constraint, reducing power output
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacked architecture, with inductors, capacitors, and driver chips arranged in multiple layers connected via through-silicon vias (TSVs). This vertical integration enables significantly larger inductor footprints without increasing the module's planar area, directly resolving the contradiction between power output and inductor size constraints.
2Ease of manufacture
If the conventional integration method is used, then the power supply module can be assembled, but the wiring becomes difficult and complex, increasing device complexity
Solution Approach 1:
The patent employs vertical stacking with TSV connections to replace complex planar wiring with straightforward vertical interconnections. The through-silicon vias provide direct electrical pathways between layers, dramatically simplifying the wiring architecture and reducing manufacturing complexity compared to conventional planar routing.
Solution Approach 2:
The patent integrates multiple functional components (inductors, capacitors, driver chips) into a single stacked package, merging what would traditionally be separate discrete components into one unified module. This consolidation reduces the number of external connections and simplifies the overall wiring architecture.
3Loss of substance
If the conventional integration method limits inductor size, then the module size can be controlled, but the utilization rate of inductor and capacitor materials decreases, affecting accuracy and cost
Solution Approach 1:
The patent utilizes vertical space through multi-layer stacking to maximize the effective use of inductor and capacitor materials. By arranging components in three dimensions rather than two, the design achieves high material utilization rates without proportionally increasing the module's planar footprint, directly addressing the material efficiency concern.
Data Source
AI summary
A device module includes first and conductive second conductive layers, and first and second functional layers between the first and second conductive layers. The first functional layer includes a plurality of capacitors and a plurality of via electrodes isolated from the plurality of capacitors. A plurality of inductors are formed in the second functional layer, each arranged along a thickness direction of the second functional layer. Thus, a first terminal of the inductor is electrically coupled with the first conductive layer through corresponding one of the via electrodes, and a second terminal of the inductor is electrically coupled with the second conductive layer. The device module simplifies the layout and wiring of a multi-phase circuit by directly installing the driver on the multi-inductor array with the pins being arranged longitudinally, and improves the effective utilization of inductor and capacitor materials.